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@@ -3084,7 +3084,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
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intel_crtc->dspaddr_offset =
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intel_compute_tile_offset(&x, &y, plane_state, 0);
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- if (rotation == DRM_ROTATE_180) {
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+ if (rotation & DRM_ROTATE_180) {
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dspcntr |= DISPPLANE_ROTATE_180;
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x += (crtc_state->pipe_src_w - 1);
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@@ -3188,7 +3188,7 @@ static void ironlake_update_primary_plane(struct drm_plane *primary,
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intel_crtc->dspaddr_offset =
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intel_compute_tile_offset(&x, &y, plane_state, 0);
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- if (rotation == DRM_ROTATE_180) {
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+ if (rotation & DRM_ROTATE_180) {
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dspcntr |= DISPPLANE_ROTATE_180;
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if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
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@@ -10881,7 +10881,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
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if (HAS_DDI(dev_priv))
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cntl |= CURSOR_PIPE_CSC_ENABLE;
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- if (plane_state->base.rotation == DRM_ROTATE_180)
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+ if (plane_state->base.rotation & DRM_ROTATE_180)
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cntl |= CURSOR_ROTATE_180;
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}
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@@ -10927,7 +10927,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
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/* ILK+ do this automagically */
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if (HAS_GMCH_DISPLAY(dev_priv) &&
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- plane_state->base.rotation == DRM_ROTATE_180) {
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+ plane_state->base.rotation & DRM_ROTATE_180) {
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base += (plane_state->base.crtc_h *
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plane_state->base.crtc_w - 1) * 4;
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}
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