|
@@ -684,15 +684,22 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
|
|
|
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
|
|
|
struct dc_link *link = pipe_ctx->stream->sink->link;
|
|
|
|
|
|
- /* 1. update AVI info frame (HDMI, DP)
|
|
|
- * we always need to update info frame
|
|
|
- */
|
|
|
+
|
|
|
uint32_t active_total_with_borders;
|
|
|
uint32_t early_control = 0;
|
|
|
struct timing_generator *tg = pipe_ctx->stream_res.tg;
|
|
|
|
|
|
- /* TODOFPGA may change to hwss.update_info_frame */
|
|
|
+ /* For MST, there are multiply stream go to only one link.
|
|
|
+ * connect DIG back_end to front_end while enable_stream and
|
|
|
+ * disconnect them during disable_stream
|
|
|
+ * BY this, it is logic clean to separate stream and link */
|
|
|
+ link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
|
|
|
+ pipe_ctx->stream_res.stream_enc->id, true);
|
|
|
+
|
|
|
+ /* update AVI info frame (HDMI, DP)*/
|
|
|
+ /* TODO: FPGA may change to hwss.update_info_frame */
|
|
|
dce110_update_info_frame(pipe_ctx);
|
|
|
+
|
|
|
/* enable early control to avoid corruption on DP monitor*/
|
|
|
active_total_with_borders =
|
|
|
timing->h_addressable
|
|
@@ -713,12 +720,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
|
|
|
pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
|
|
|
}
|
|
|
|
|
|
- /* For MST, there are multiply stream go to only one link.
|
|
|
- * connect DIG back_end to front_end while enable_stream and
|
|
|
- * disconnect them during disable_stream
|
|
|
- * BY this, it is logic clean to separate stream and link */
|
|
|
- link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
|
|
|
- pipe_ctx->stream_res.stream_enc->id, true);
|
|
|
+
|
|
|
+
|
|
|
|
|
|
}
|
|
|
|