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@@ -150,35 +150,35 @@ enum chip_register_bits {
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enum pci_interrupt_cause {
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enum pci_interrupt_cause {
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/* MAIN_IRQ_CAUSE (R10200) Bits*/
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/* MAIN_IRQ_CAUSE (R10200) Bits*/
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- IRQ_COM_IN_I2O_IOP0 = (1 << 0),
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- IRQ_COM_IN_I2O_IOP1 = (1 << 1),
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- IRQ_COM_IN_I2O_IOP2 = (1 << 2),
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- IRQ_COM_IN_I2O_IOP3 = (1 << 3),
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- IRQ_COM_OUT_I2O_HOS0 = (1 << 4),
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- IRQ_COM_OUT_I2O_HOS1 = (1 << 5),
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- IRQ_COM_OUT_I2O_HOS2 = (1 << 6),
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- IRQ_COM_OUT_I2O_HOS3 = (1 << 7),
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- IRQ_PCIF_TO_CPU_DRBL0 = (1 << 8),
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- IRQ_PCIF_TO_CPU_DRBL1 = (1 << 9),
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- IRQ_PCIF_TO_CPU_DRBL2 = (1 << 10),
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- IRQ_PCIF_TO_CPU_DRBL3 = (1 << 11),
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- IRQ_PCIF_DRBL0 = (1 << 12),
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- IRQ_PCIF_DRBL1 = (1 << 13),
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- IRQ_PCIF_DRBL2 = (1 << 14),
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- IRQ_PCIF_DRBL3 = (1 << 15),
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- IRQ_XOR_A = (1 << 16),
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- IRQ_XOR_B = (1 << 17),
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- IRQ_SAS_A = (1 << 18),
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- IRQ_SAS_B = (1 << 19),
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- IRQ_CPU_CNTRL = (1 << 20),
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- IRQ_GPIO = (1 << 21),
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- IRQ_UART = (1 << 22),
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- IRQ_SPI = (1 << 23),
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- IRQ_I2C = (1 << 24),
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- IRQ_SGPIO = (1 << 25),
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- IRQ_COM_ERR = (1 << 29),
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- IRQ_I2O_ERR = (1 << 30),
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- IRQ_PCIE_ERR = (1 << 31),
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+ MVS_IRQ_COM_IN_I2O_IOP0 = (1 << 0),
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+ MVS_IRQ_COM_IN_I2O_IOP1 = (1 << 1),
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+ MVS_IRQ_COM_IN_I2O_IOP2 = (1 << 2),
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+ MVS_IRQ_COM_IN_I2O_IOP3 = (1 << 3),
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+ MVS_IRQ_COM_OUT_I2O_HOS0 = (1 << 4),
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+ MVS_IRQ_COM_OUT_I2O_HOS1 = (1 << 5),
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+ MVS_IRQ_COM_OUT_I2O_HOS2 = (1 << 6),
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+ MVS_IRQ_COM_OUT_I2O_HOS3 = (1 << 7),
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+ MVS_IRQ_PCIF_TO_CPU_DRBL0 = (1 << 8),
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+ MVS_IRQ_PCIF_TO_CPU_DRBL1 = (1 << 9),
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+ MVS_IRQ_PCIF_TO_CPU_DRBL2 = (1 << 10),
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+ MVS_IRQ_PCIF_TO_CPU_DRBL3 = (1 << 11),
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+ MVS_IRQ_PCIF_DRBL0 = (1 << 12),
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+ MVS_IRQ_PCIF_DRBL1 = (1 << 13),
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+ MVS_IRQ_PCIF_DRBL2 = (1 << 14),
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+ MVS_IRQ_PCIF_DRBL3 = (1 << 15),
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+ MVS_IRQ_XOR_A = (1 << 16),
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+ MVS_IRQ_XOR_B = (1 << 17),
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+ MVS_IRQ_SAS_A = (1 << 18),
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+ MVS_IRQ_SAS_B = (1 << 19),
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+ MVS_IRQ_CPU_CNTRL = (1 << 20),
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+ MVS_IRQ_GPIO = (1 << 21),
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+ MVS_IRQ_UART = (1 << 22),
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+ MVS_IRQ_SPI = (1 << 23),
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+ MVS_IRQ_I2C = (1 << 24),
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+ MVS_IRQ_SGPIO = (1 << 25),
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+ MVS_IRQ_COM_ERR = (1 << 29),
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+ MVS_IRQ_I2O_ERR = (1 << 30),
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+ MVS_IRQ_PCIE_ERR = (1 << 31),
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};
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};
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union reg_phy_cfg {
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union reg_phy_cfg {
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