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@@ -66,7 +66,6 @@ struct sh_cmt_device;
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enum sh_cmt_model {
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SH_CMT_16BIT,
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SH_CMT_32BIT,
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- SH_CMT_32BIT_FAST,
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SH_CMT_48BIT,
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SH_CMT0_RCAR_GEN2,
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SH_CMT1_RCAR_GEN2,
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@@ -203,16 +202,6 @@ static const struct sh_cmt_info sh_cmt_info[] = {
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.read_count = sh_cmt_read32,
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.write_count = sh_cmt_write32,
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},
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- [SH_CMT_32BIT_FAST] = {
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- .model = SH_CMT_32BIT_FAST,
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- .width = 32,
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- .overflow_bit = SH_CMT32_CMCSR_CMF,
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- .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
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- .read_control = sh_cmt_read16,
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- .write_control = sh_cmt_write16,
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- .read_count = sh_cmt_read32,
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- .write_count = sh_cmt_write32,
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- },
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[SH_CMT_48BIT] = {
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.model = SH_CMT_48BIT,
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.channels_mask = 0x3f,
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@@ -890,13 +879,6 @@ static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
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case SH_CMT_48BIT:
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ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
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break;
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- case SH_CMT_32BIT_FAST:
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- /*
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- * The 32-bit "fast" timer has a single channel at hwidx 5 but
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- * is located at offset 0x40 instead of 0x60 for some reason.
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- */
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- ch->ioctrl = cmt->mapbase + 0x40;
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- break;
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case SH_CMT0_RCAR_GEN2:
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case SH_CMT1_RCAR_GEN2:
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ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
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@@ -952,8 +934,6 @@ static const struct platform_device_id sh_cmt_id_table[] = {
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MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
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static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
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- { .compatible = "renesas,cmt-32", .data = &sh_cmt_info[SH_CMT_32BIT] },
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- { .compatible = "renesas,cmt-32-fast", .data = &sh_cmt_info[SH_CMT_32BIT_FAST] },
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{ .compatible = "renesas,cmt-48", .data = &sh_cmt_info[SH_CMT_48BIT] },
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{ .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] },
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{ .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] },
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