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@@ -148,7 +148,8 @@ nvbios_dpcfg_entry(struct nvkm_bios *bios, u16 outp, u8 idx,
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outp = nvbios_dp_table(bios, ver, hdr, cnt, len);
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outp = nvbios_dp_table(bios, ver, hdr, cnt, len);
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*hdr = *hdr + (*len * * cnt);
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*hdr = *hdr + (*len * * cnt);
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*len = nv_ro08(bios, outp + 0x06);
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*len = nv_ro08(bios, outp + 0x06);
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- *cnt = nv_ro08(bios, outp + 0x07);
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+ *cnt = nv_ro08(bios, outp + 0x07) *
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+ nv_ro08(bios, outp + 0x05);
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}
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}
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if (idx < *cnt)
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if (idx < *cnt)
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@@ -196,12 +197,10 @@ nvbios_dpcfg_match(struct nvkm_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe,
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u16 data;
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u16 data;
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if (*ver >= 0x30) {
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if (*ver >= 0x30) {
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- /*XXX: there's a second set of these on at least 4.1, that
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- * i've witnessed nvidia using instead of the first
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- * on gm204. figure out what/why
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- */
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const u8 vsoff[] = { 0, 4, 7, 9 };
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const u8 vsoff[] = { 0, 4, 7, 9 };
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idx = (pc * 10) + vsoff[vs] + pe;
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idx = (pc * 10) + vsoff[vs] + pe;
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+ if (*ver >= 0x40 && *hdr >= 0x12)
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+ idx += nv_ro08(bios, outp + 0x11) * 40;
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} else {
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} else {
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while ((data = nvbios_dpcfg_entry(bios, outp, ++idx,
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while ((data = nvbios_dpcfg_entry(bios, outp, ++idx,
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ver, hdr, cnt, len))) {
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ver, hdr, cnt, len))) {
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Ben Skeggs