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@@ -92,13 +92,13 @@
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/* Last Converted Data Register */
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#define AT91_SAMA5D2_LCDR 0x20
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/* Interrupt Enable Register */
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-#define AT91_SAMA5D2_IER 0x24
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+#define AT91_SAMA5D2_IER 0x24
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/* Interrupt Disable Register */
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-#define AT91_SAMA5D2_IDR 0x28
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+#define AT91_SAMA5D2_IDR 0x28
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/* Interrupt Mask Register */
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-#define AT91_SAMA5D2_IMR 0x2c
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+#define AT91_SAMA5D2_IMR 0x2c
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/* Interrupt Status Register */
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-#define AT91_SAMA5D2_ISR 0x30
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+#define AT91_SAMA5D2_ISR 0x30
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/* Last Channel Trigger Mode Register */
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#define AT91_SAMA5D2_LCTMR 0x34
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/* Last Channel Compare Window Register */
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@@ -106,17 +106,17 @@
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/* Overrun Status Register */
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#define AT91_SAMA5D2_OVER 0x3c
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/* Extended Mode Register */
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-#define AT91_SAMA5D2_EMR 0x40
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+#define AT91_SAMA5D2_EMR 0x40
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/* Compare Window Register */
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-#define AT91_SAMA5D2_CWR 0x44
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+#define AT91_SAMA5D2_CWR 0x44
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/* Channel Gain Register */
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-#define AT91_SAMA5D2_CGR 0x48
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+#define AT91_SAMA5D2_CGR 0x48
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/* Channel Offset Register */
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-#define AT91_SAMA5D2_COR 0x4c
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+#define AT91_SAMA5D2_COR 0x4c
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/* Channel Data Register 0 */
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#define AT91_SAMA5D2_CDR0 0x50
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/* Analog Control Register */
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-#define AT91_SAMA5D2_ACR 0x94
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+#define AT91_SAMA5D2_ACR 0x94
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/* Touchscreen Mode Register */
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#define AT91_SAMA5D2_TSMR 0xb0
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/* Touchscreen X Position Register */
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@@ -130,7 +130,7 @@
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/* Correction Select Register */
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#define AT91_SAMA5D2_COSR 0xd0
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/* Correction Value Register */
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-#define AT91_SAMA5D2_CVR 0xd4
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+#define AT91_SAMA5D2_CVR 0xd4
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/* Channel Error Correction Register */
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#define AT91_SAMA5D2_CECR 0xd8
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/* Write Protection Mode Register */
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