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@@ -1044,14 +1044,14 @@ static enum dc_status apply_single_controller_ctx_to_hw(
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/* */
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/* */
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dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
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dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
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- pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
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- pipe_ctx->stream_res.opp,
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- COLOR_SPACE_YCBCR601,
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- stream->timing.display_color_depth,
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- pipe_ctx->stream->signal);
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-
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/* FPGA does not program backend */
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/* FPGA does not program backend */
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if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
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if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
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+ pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
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+ pipe_ctx->stream_res.opp,
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+ COLOR_SPACE_YCBCR601,
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+ stream->timing.display_color_depth,
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+ pipe_ctx->stream->signal);
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+
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pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
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pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
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pipe_ctx->stream_res.opp,
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pipe_ctx->stream_res.opp,
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&stream->bit_depth_params,
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&stream->bit_depth_params,
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@@ -1064,6 +1064,11 @@ static enum dc_status apply_single_controller_ctx_to_hw(
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BREAK_TO_DEBUGGER();
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BREAK_TO_DEBUGGER();
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return DC_ERROR_UNEXPECTED;
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return DC_ERROR_UNEXPECTED;
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}
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}
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+ pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
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+ pipe_ctx->stream_res.opp,
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+ COLOR_SPACE_YCBCR601,
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+ stream->timing.display_color_depth,
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+ pipe_ctx->stream->signal);
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if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
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if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
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stream->sink->link->link_enc->funcs->setup(
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stream->sink->link->link_enc->funcs->setup(
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