|
@@ -37,7 +37,6 @@
|
|
|
#include <asm/mbus.h>
|
|
|
#include <asm/page.h>
|
|
|
#include <asm/asi.h>
|
|
|
-#include <asm/msi.h>
|
|
|
#include <asm/smp.h>
|
|
|
#include <asm/io.h>
|
|
|
|
|
@@ -116,6 +115,25 @@ static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
|
|
|
set_pte((pte_t *)ctxp, pte);
|
|
|
}
|
|
|
|
|
|
+/*
|
|
|
+ * Locations of MSI Registers.
|
|
|
+ */
|
|
|
+#define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */
|
|
|
+
|
|
|
+/*
|
|
|
+ * Useful bits in the MSI Registers.
|
|
|
+ */
|
|
|
+#define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */
|
|
|
+
|
|
|
+static void msi_set_sync(void)
|
|
|
+{
|
|
|
+ __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
|
|
|
+ "andn %%g3, %2, %%g3\n\t"
|
|
|
+ "sta %%g3, [%0] %1\n\t" : :
|
|
|
+ "r" (MSI_MBUS_ARBEN),
|
|
|
+ "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
|
|
|
+}
|
|
|
+
|
|
|
void pmd_set(pmd_t *pmdp, pte_t *ptep)
|
|
|
{
|
|
|
unsigned long ptp; /* Physical address, shifted right by 4 */
|