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@@ -84,6 +84,7 @@ enum sst_hsw_device_mclk {
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enum sst_hsw_device_mode {
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SST_HSW_DEVICE_CLOCK_SLAVE = 0,
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SST_HSW_DEVICE_CLOCK_MASTER = 1,
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+ SST_HSW_DEVICE_TDM_CLOCK_MASTER = 2,
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};
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/* DX Power State */
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@@ -295,7 +296,8 @@ struct sst_hsw_ipc_device_config_req {
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u32 clock_frequency;
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u32 mode;
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u16 clock_divider;
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- u16 reserved;
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+ u8 channels;
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+ u8 reserved;
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} __attribute__((packed));
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/* Audio Data formats */
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