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@@ -881,7 +881,7 @@ static int gasket_perform_mapping(
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u64 off =
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(u64)host_addr -
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(u64)pg_tbl->coherent_pages[0].user_virt;
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- ptes[i].page = 0;
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+ ptes[i].page = NULL;
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ptes[i].offset = offset;
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ptes[i].dma_addr = pg_tbl->coherent_pages[0].paddr +
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off + i * PAGE_SIZE;
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@@ -1740,7 +1740,7 @@ int gasket_free_coherent_memory(struct gasket_dev *gasket_dev, u64 size,
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gasket_dev->coherent_buffer.virt_base,
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gasket_dev->coherent_buffer.phys_base);
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gasket_dev->coherent_buffer.length_bytes = 0;
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- gasket_dev->coherent_buffer.virt_base = 0;
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+ gasket_dev->coherent_buffer.virt_base = NULL;
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gasket_dev->coherent_buffer.phys_base = 0;
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}
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return 0;
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@@ -1765,7 +1765,7 @@ void gasket_free_coherent_memory_all(
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gasket_dev->coherent_buffer.virt_base,
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gasket_dev->coherent_buffer.phys_base);
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gasket_dev->coherent_buffer.length_bytes = 0;
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- gasket_dev->coherent_buffer.virt_base = 0;
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+ gasket_dev->coherent_buffer.virt_base = NULL;
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gasket_dev->coherent_buffer.phys_base = 0;
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}
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}
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