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@@ -4212,6 +4212,18 @@ static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
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}
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+static void gfx_v7_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
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+{
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+ struct amdgpu_device *adev = ring->adev;
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+ uint32_t value = 0;
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+
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+ value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
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+ value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
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+ value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
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+ value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
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+ WREG32(mmSQ_CMD, value);
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+}
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+
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static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
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{
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WREG32(mmSQ_IND_INDEX,
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@@ -5088,6 +5100,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
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.pad_ib = amdgpu_ring_generic_pad_ib,
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.emit_cntxcntl = gfx_v7_ring_emit_cntxcntl,
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.emit_wreg = gfx_v7_0_ring_emit_wreg,
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+ .soft_recovery = gfx_v7_0_ring_soft_recovery,
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};
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static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
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