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@@ -307,6 +307,12 @@ static const struct counter_desc pport_eth_ext_stats_desc[] = {
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MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
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MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
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counter_set.pcie_perf_cntrs_grp_data_layout.c)
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counter_set.pcie_perf_cntrs_grp_data_layout.c)
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+#define PCIE_PERF_OFF64(c) \
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+ MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
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+#define PCIE_PERF_GET64(pcie_stats, c) \
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+ MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
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+ counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
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+
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struct mlx5e_pcie_stats {
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struct mlx5e_pcie_stats {
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__be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
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__be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
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};
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};
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@@ -316,6 +322,10 @@ static const struct counter_desc pcie_perf_stats_desc[] = {
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{ "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
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{ "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
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};
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};
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+static const struct counter_desc pcie_perf_stats_desc64[] = {
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+ { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) },
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+};
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+
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static const struct counter_desc pcie_perf_stall_stats_desc[] = {
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static const struct counter_desc pcie_perf_stall_stats_desc[] = {
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{ "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
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{ "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
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{ "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
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{ "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
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@@ -415,6 +425,9 @@ static const struct counter_desc sq_stats_desc[] = {
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#define NUM_PCIE_PERF_COUNTERS(priv) \
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#define NUM_PCIE_PERF_COUNTERS(priv) \
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(ARRAY_SIZE(pcie_perf_stats_desc) * \
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(ARRAY_SIZE(pcie_perf_stats_desc) * \
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MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
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MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
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+#define NUM_PCIE_PERF_COUNTERS64(priv) \
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+ (ARRAY_SIZE(pcie_perf_stats_desc64) * \
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+ MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
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#define NUM_PCIE_PERF_STALL_COUNTERS(priv) \
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#define NUM_PCIE_PERF_STALL_COUNTERS(priv) \
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(ARRAY_SIZE(pcie_perf_stall_stats_desc) * \
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(ARRAY_SIZE(pcie_perf_stall_stats_desc) * \
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MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
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MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
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@@ -433,6 +446,7 @@ static const struct counter_desc sq_stats_desc[] = {
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NUM_PPORT_PRIO + \
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NUM_PPORT_PRIO + \
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NUM_PPORT_ETH_EXT_COUNTERS(priv))
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NUM_PPORT_ETH_EXT_COUNTERS(priv))
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#define NUM_PCIE_COUNTERS(priv) (NUM_PCIE_PERF_COUNTERS(priv) + \
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#define NUM_PCIE_COUNTERS(priv) (NUM_PCIE_PERF_COUNTERS(priv) + \
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+ NUM_PCIE_PERF_COUNTERS64(priv) +\
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NUM_PCIE_PERF_STALL_COUNTERS(priv))
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NUM_PCIE_PERF_STALL_COUNTERS(priv))
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#define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
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#define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
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#define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
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#define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
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