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@@ -118,3 +118,59 @@ Example:
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other nodes ...
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};
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+
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+
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+USB3 core reset
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+---------------
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+
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+USB3 core reset belongs to USB3 glue layer. Before using the core reset,
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+it is necessary to control the clocks and resets to enable this layer.
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+These clocks and resets should be described in each property.
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+
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+Required properties:
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+- compatible: Should be
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+ "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC
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+ "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC
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+ "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC
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+ "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC
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+- #reset-cells: Should be 1.
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+- reg: Specifies offset and length of the register set for the device.
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+- clocks: A list of phandles to the clock gate for USB3 glue layer.
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+ According to the clock-names, appropriate clocks are required.
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+- clock-names: Should contain
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+ "gio", "link" - for Pro4 SoC
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+ "link" - for others
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+- resets: A list of phandles to the reset control for USB3 glue layer.
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+ According to the reset-names, appropriate resets are required.
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+- reset-names: Should contain
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+ "gio", "link" - for Pro4 SoC
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+ "link" - for others
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+
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+Example:
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+
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+ usb-glue@65b00000 {
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+ compatible = "socionext,uniphier-ld20-dwc3-glue",
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+ "simple-mfd";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 0x65b00000 0x400>;
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+
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+ usb_rst: reset@0 {
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+ compatible = "socionext,uniphier-ld20-usb3-reset";
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+ reg = <0x0 0x4>;
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+ #reset-cells = <1>;
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+ clock-names = "link";
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+ clocks = <&sys_clk 14>;
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+ reset-names = "link";
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+ resets = <&sys_rst 14>;
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+ };
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+
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+ regulator {
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+ ...
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+ };
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+
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+ phy {
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+ ...
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+ };
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+ ...
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+ };
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