|
@@ -1,7 +1,7 @@
|
|
|
/* SPDX-License-Identifier: GPL-2.0 */
|
|
|
/*
|
|
|
* File: portdrv.h
|
|
|
- * Purpose: PCI Express Port Bus Driver's Internal Data Structures
|
|
|
+ * Purpose: PCI Express Port Bus Driver's Data Structures
|
|
|
*
|
|
|
* Copyright (C) 2004 Intel
|
|
|
* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
|
|
@@ -12,7 +12,66 @@
|
|
|
|
|
|
#include <linux/compiler.h>
|
|
|
|
|
|
+/* Service Type */
|
|
|
+#define PCIE_PORT_SERVICE_PME_SHIFT 0 /* Power Management Event */
|
|
|
+#define PCIE_PORT_SERVICE_PME (1 << PCIE_PORT_SERVICE_PME_SHIFT)
|
|
|
+#define PCIE_PORT_SERVICE_AER_SHIFT 1 /* Advanced Error Reporting */
|
|
|
+#define PCIE_PORT_SERVICE_AER (1 << PCIE_PORT_SERVICE_AER_SHIFT)
|
|
|
+#define PCIE_PORT_SERVICE_HP_SHIFT 2 /* Native Hotplug */
|
|
|
+#define PCIE_PORT_SERVICE_HP (1 << PCIE_PORT_SERVICE_HP_SHIFT)
|
|
|
+#define PCIE_PORT_SERVICE_VC_SHIFT 3 /* Virtual Channel */
|
|
|
+#define PCIE_PORT_SERVICE_VC (1 << PCIE_PORT_SERVICE_VC_SHIFT)
|
|
|
+#define PCIE_PORT_SERVICE_DPC_SHIFT 4 /* Downstream Port Containment */
|
|
|
+#define PCIE_PORT_SERVICE_DPC (1 << PCIE_PORT_SERVICE_DPC_SHIFT)
|
|
|
+
|
|
|
#define PCIE_PORT_DEVICE_MAXSERVICES 5
|
|
|
+
|
|
|
+/* Port Type */
|
|
|
+#define PCIE_ANY_PORT (~0)
|
|
|
+
|
|
|
+struct pcie_device {
|
|
|
+ int irq; /* Service IRQ/MSI/MSI-X Vector */
|
|
|
+ struct pci_dev *port; /* Root/Upstream/Downstream Port */
|
|
|
+ u32 service; /* Port service this device represents */
|
|
|
+ void *priv_data; /* Service Private Data */
|
|
|
+ struct device device; /* Generic Device Interface */
|
|
|
+};
|
|
|
+#define to_pcie_device(d) container_of(d, struct pcie_device, device)
|
|
|
+
|
|
|
+static inline void set_service_data(struct pcie_device *dev, void *data)
|
|
|
+{
|
|
|
+ dev->priv_data = data;
|
|
|
+}
|
|
|
+
|
|
|
+static inline void *get_service_data(struct pcie_device *dev)
|
|
|
+{
|
|
|
+ return dev->priv_data;
|
|
|
+}
|
|
|
+
|
|
|
+struct pcie_port_service_driver {
|
|
|
+ const char *name;
|
|
|
+ int (*probe) (struct pcie_device *dev);
|
|
|
+ void (*remove) (struct pcie_device *dev);
|
|
|
+ int (*suspend) (struct pcie_device *dev);
|
|
|
+ int (*resume) (struct pcie_device *dev);
|
|
|
+
|
|
|
+ /* Device driver may resume normal operations */
|
|
|
+ void (*error_resume)(struct pci_dev *dev);
|
|
|
+
|
|
|
+ /* Link Reset Capability - AER service driver specific */
|
|
|
+ pci_ers_result_t (*reset_link) (struct pci_dev *dev);
|
|
|
+
|
|
|
+ int port_type; /* Type of the port this driver can handle */
|
|
|
+ u32 service; /* Port service this device represents */
|
|
|
+
|
|
|
+ struct device_driver driver;
|
|
|
+};
|
|
|
+#define to_service_driver(d) \
|
|
|
+ container_of(d, struct pcie_port_service_driver, driver)
|
|
|
+
|
|
|
+int pcie_port_service_register(struct pcie_port_service_driver *new);
|
|
|
+void pcie_port_service_unregister(struct pcie_port_service_driver *new);
|
|
|
+
|
|
|
/*
|
|
|
* The PCIe Capability Interrupt Message Number (PCIe r3.1, sec 7.8.2) must
|
|
|
* be one of the first 32 MSI-X entries. Per PCI r3.0, sec 6.8.3.1, MSI
|