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@@ -52,6 +52,8 @@
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#define VCE_V3_0_STACK_SIZE (64 * 1024)
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#define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024))
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+#define FW_52_8_3 ((52 << 24) | (8 << 16) | (3 << 8))
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+
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static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx);
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static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
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static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
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@@ -382,6 +384,10 @@ static int vce_v3_0_sw_init(void *handle)
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if (r)
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return r;
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+ /* 52.8.3 required for 3 ring support */
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+ if (adev->vce.fw_version < FW_52_8_3)
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+ adev->vce.num_rings = 2;
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+
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r = amdgpu_vce_resume(adev);
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if (r)
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return r;
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