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@@ -64,6 +64,56 @@ Required properties:
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first port should be the input endpoint. The second should be the
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output, usually to an HDMI connector.
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+DWC HDMI TX Encoder
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+-------------------
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+
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+The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
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+with Allwinner's own PHY IP. It supports audio and video outputs and CEC.
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+
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+These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
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+Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
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+following device-specific properties.
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+
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+Required properties:
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+
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+ - compatible: value must be one of:
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+ * "allwinner,sun8i-a83t-dw-hdmi"
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+ - reg: base address and size of memory-mapped region
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+ - reg-io-width: See dw_hdmi.txt. Shall be 1.
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+ - interrupts: HDMI interrupt number
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+ - clocks: phandles to the clocks feeding the HDMI encoder
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+ * iahb: the HDMI bus clock
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+ * isfr: the HDMI register clock
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+ * tmds: TMDS clock
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+ - clock-names: the clock names mentioned above
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+ - resets: phandle to the reset controller
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+ - reset-names: must be "ctrl"
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+ - phys: phandle to the DWC HDMI PHY
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+ - phy-names: must be "phy"
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+
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+ - ports: A ports node with endpoint definitions as defined in
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+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
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+ first port should be the input endpoint. The second should be the
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+ output, usually to an HDMI connector.
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+
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+DWC HDMI PHY
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+------------
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+
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+Required properties:
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+ - compatible: value must be one of:
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+ * allwinner,sun8i-a83t-hdmi-phy
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+ * allwinner,sun8i-h3-hdmi-phy
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+ - reg: base address and size of memory-mapped region
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+ - clocks: phandles to the clocks feeding the HDMI PHY
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+ * bus: the HDMI PHY interface clock
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+ * mod: the HDMI PHY module clock
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+ - clock-names: the clock names mentioned above
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+ - resets: phandle to the reset controller driving the PHY
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+ - reset-names: must be "phy"
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+
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+H3 HDMI PHY requires additional clock:
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+ - pll-0: parent of phy clock
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+
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TV Encoder
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----------
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@@ -94,24 +144,29 @@ Required properties:
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* allwinner,sun7i-a20-tcon
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* allwinner,sun8i-a33-tcon
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* allwinner,sun8i-a83t-tcon-lcd
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+ * allwinner,sun8i-a83t-tcon-tv
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* allwinner,sun8i-v3s-tcon
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+ * allwinner,sun9i-a80-tcon-lcd
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+ * allwinner,sun9i-a80-tcon-tv
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- reg: base address and size of memory-mapped region
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- interrupts: interrupt associated to this IP
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- - clocks: phandles to the clocks feeding the TCON. Three are needed:
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+ - clocks: phandles to the clocks feeding the TCON.
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- 'ahb': the interface clocks
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- - 'tcon-ch0': The clock driving the TCON channel 0
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+ - 'tcon-ch0': The clock driving the TCON channel 0, if supported
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- resets: phandles to the reset controllers driving the encoder
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- - "lcd": the reset line for the TCON channel 0
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+ - "lcd": the reset line for the TCON
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+ - "edp": the reset line for the eDP block (A80 only)
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- clock-names: the clock names mentioned above
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- reset-names: the reset names mentioned above
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- - clock-output-names: Name of the pixel clock created
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+ - clock-output-names: Name of the pixel clock created, if TCON supports
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+ channel 0.
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoint, the second one the output
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- The output may have multiple endpoints. The TCON has two channels,
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+ The output may have multiple endpoints. TCON can have 1 or 2 channels,
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usually with the first channel being used for the panels interfaces
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(RGB, LVDS, etc.), and the second being used for the outputs that
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require another controller (TV Encoder, HDMI, etc.). The endpoints
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@@ -119,11 +174,13 @@ Required properties:
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channel the endpoint is associated to. If that property is not
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present, the endpoint number will be used as the channel number.
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-On SoCs other than the A33 and V3s, there is one more clock required:
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+For TCONs with channel 0, there is one more clock required:
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+ - 'tcon-ch0': The clock driving the TCON channel 0
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+For TCONs with channel 1, there is one more clock required:
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- 'tcon-ch1': The clock driving the TCON channel 1
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-On SoCs that support LVDS (all SoCs but the A13, H3, H5 and V3s), you
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-need one more reset line:
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+When TCON support LVDS (all TCONs except TV TCON on A83T and those found
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+in A13, H3, H5 and V3s SoCs), you need one more reset line:
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- 'lvds': The reset line driving the LVDS logic
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And on the A23, A31, A31s and A33, you need one more clock line:
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@@ -134,7 +191,7 @@ DRC
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---
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The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
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-(A31, A23, A33), allows to dynamically adjust pixel
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+(A31, A23, A33, A80), allows to dynamically adjust pixel
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brightness/contrast based on histogram measurements for LCD content
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adaptive backlight control.
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@@ -144,6 +201,7 @@ Required properties:
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* allwinner,sun6i-a31-drc
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* allwinner,sun6i-a31s-drc
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* allwinner,sun8i-a33-drc
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+ * allwinner,sun9i-a80-drc
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- reg: base address and size of the memory-mapped region.
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the DRC
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@@ -170,6 +228,7 @@ Required properties:
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* allwinner,sun6i-a31-display-backend
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* allwinner,sun7i-a20-display-backend
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* allwinner,sun8i-a33-display-backend
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+ * allwinner,sun9i-a80-display-backend
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- reg: base address and size of the memory-mapped region.
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the frontend and backend
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@@ -191,6 +250,28 @@ On the A33, some additional properties are required:
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- resets and reset-names need to have a phandle to the SAT bus
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resets, whose name will be "sat"
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+DEU
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+---
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+
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+The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC,
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+can sharpen the display content in both luma and chroma channels.
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+
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+Required properties:
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+ - compatible: value must be one of:
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+ * allwinner,sun9i-a80-deu
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+ - reg: base address and size of the memory-mapped region.
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+ - interrupts: interrupt associated to this IP
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+ - clocks: phandles to the clocks feeding the DEU
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+ * ahb: the DEU interface clock
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+ * mod: the DEU module clock
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+ * ram: the DEU DRAM clock
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+ - clock-names: the clock names mentioned above
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+ - resets: phandles to the reset line driving the DEU
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+
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+- ports: A ports node with endpoint definitions as defined in
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+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
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+ first port should be the input endpoints, the second one the outputs
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+
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Display Engine Frontend
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-----------------------
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@@ -204,6 +285,7 @@ Required properties:
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* allwinner,sun6i-a31-display-frontend
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* allwinner,sun7i-a20-display-frontend
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* allwinner,sun8i-a33-display-frontend
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+ * allwinner,sun9i-a80-display-frontend
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- reg: base address and size of the memory-mapped region.
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the frontend and backend
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@@ -226,6 +308,8 @@ supported.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun8i-a83t-de2-mixer-0
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+ * allwinner,sun8i-a83t-de2-mixer-1
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+ * allwinner,sun8i-h3-de2-mixer-0
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* allwinner,sun8i-v3s-de2-mixer
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- reg: base address and size of the memory-mapped region.
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- clocks: phandles to the clocks feeding the mixer
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@@ -256,7 +340,9 @@ Required properties:
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* allwinner,sun7i-a20-display-engine
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* allwinner,sun8i-a33-display-engine
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* allwinner,sun8i-a83t-display-engine
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+ * allwinner,sun8i-h3-display-engine
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* allwinner,sun8i-v3s-display-engine
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+ * allwinner,sun9i-a80-display-engine
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- allwinner,pipelines: list of phandle to the display engine
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frontends (DE 1.0) or mixers (DE 2.0) available.
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