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@@ -3666,19 +3666,11 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
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*
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* The 82599 supports FLR on VFs, but FLR support is reported only
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* in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
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- * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
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+ * Thus we must call pcie_flr() directly without first checking if it is
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+ * supported.
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*/
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-
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- if (probe)
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- return 0;
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-
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- if (!pci_wait_for_pending_transaction(dev))
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- dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
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-
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- pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
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-
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- msleep(100);
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-
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+ if (!probe)
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+ pcie_flr(dev);
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return 0;
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}
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@@ -3783,20 +3775,7 @@ static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
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PCI_MSIX_FLAGS_ENABLE |
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PCI_MSIX_FLAGS_MASKALL);
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- /*
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- * Start of pcie_flr() code sequence. This reset code is a copy of
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- * the guts of pcie_flr() because that's not an exported function.
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- */
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-
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- if (!pci_wait_for_pending_transaction(dev))
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- dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
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-
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- pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
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- msleep(100);
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-
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- /*
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- * End of pcie_flr() code sequence.
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- */
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+ pcie_flr(dev);
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/*
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* Restore the configuration information (BAR values, etc.) including
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@@ -4677,3 +4656,11 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2030, quirk_no_aersid);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);
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+
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+/* FLR may cause some 82579 devices to hang. */
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+static void quirk_intel_no_flr(struct pci_dev *dev)
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+{
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+ dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
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+}
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
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