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@@ -1310,6 +1310,16 @@ void i915_check_and_clear_faults(struct drm_device *dev)
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POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
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}
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+static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
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+{
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+ if (INTEL_INFO(dev_priv->dev)->gen < 6) {
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+ intel_gtt_chipset_flush();
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+ } else {
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+ I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
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+ POSTING_READ(GFX_FLSH_CNTL_GEN6);
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+ }
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+}
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+
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void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@@ -1326,6 +1336,8 @@ void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
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dev_priv->gtt.base.start,
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dev_priv->gtt.base.total,
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true);
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+
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+ i915_ggtt_flush(dev_priv);
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}
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void i915_gem_restore_gtt_mappings(struct drm_device *dev)
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@@ -1378,7 +1390,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
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gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
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}
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- i915_gem_chipset_flush(dev);
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+ i915_ggtt_flush(dev_priv);
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}
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int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
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