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@@ -280,8 +280,24 @@
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clock-div = <48>;
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clock-mult = <1>;
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};
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+ m2_clk: m2 {
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+ compatible = "fixed-factor-clock";
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+ clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
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+ #clock-cells = <0>;
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+ clock-div = <8>;
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+ clock-mult = <1>;
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+ };
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/* Gate clocks */
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+ mstp1_clks: mstp1_clks@e6150134 {
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+ compatible = "renesas,r8a7792-mstp-clocks",
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+ "renesas,cpg-mstp-clocks";
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+ reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
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+ clocks = <&m2_clk>;
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+ #clock-cells = <1>;
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+ clock-indices = <R8A7792_CLK_JPU>;
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+ clock-output-names = "jpu";
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+ };
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mstp2_clks: mstp2_clks@e6150138 {
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compatible = "renesas,r8a7792-mstp-clocks",
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"renesas,cpg-mstp-clocks";
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