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@@ -1998,14 +1998,19 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
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}
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static uint32_t
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-hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
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+hsw_compute_linetime_wm(struct drm_device *dev,
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+ struct intel_crtc_state *cstate)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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- const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
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+ const struct drm_display_mode *adjusted_mode =
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+ &cstate->base.adjusted_mode;
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u32 linetime, ips_linetime;
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- if (!intel_crtc->active)
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+ if (!cstate->base.active)
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+ return 0;
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+ if (WARN_ON(adjusted_mode->crtc_clock == 0))
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+ return 0;
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+ if (WARN_ON(dev_priv->cdclk_freq == 0))
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return 0;
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/* The WM are computed with base on how long it takes to fill a single
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@@ -2313,8 +2318,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
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pristate, sprstate, curstate, &pipe_wm->wm[0]);
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if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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- pipe_wm->linetime = hsw_compute_linetime_wm(dev,
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- &intel_crtc->base);
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+ pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
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/* LP0 watermarks always use 1/2 DDB partitioning */
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ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
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