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@@ -461,6 +461,7 @@ union set_pixel_clock {
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PIXEL_CLOCK_PARAMETERS_V3 v3;
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PIXEL_CLOCK_PARAMETERS_V5 v5;
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PIXEL_CLOCK_PARAMETERS_V6 v6;
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+ PIXEL_CLOCK_PARAMETERS_V7 v7;
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};
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/* on DCE5, make sure the voltage is high enough to support the
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@@ -566,18 +567,18 @@ static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id)
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}
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void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
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- u32 crtc_id,
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- int pll_id,
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- u32 encoder_mode,
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- u32 encoder_id,
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- u32 clock,
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- u32 ref_div,
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- u32 fb_div,
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- u32 frac_fb_div,
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- u32 post_div,
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- int bpc,
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- bool ss_enabled,
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- struct amdgpu_atom_ss *ss)
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+ u32 crtc_id,
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+ int pll_id,
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+ u32 encoder_mode,
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+ u32 encoder_id,
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+ u32 clock,
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+ u32 ref_div,
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+ u32 fb_div,
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+ u32 frac_fb_div,
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+ u32 post_div,
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+ int bpc,
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+ bool ss_enabled,
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+ struct amdgpu_atom_ss *ss)
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{
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struct drm_device *dev = crtc->dev;
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struct amdgpu_device *adev = dev->dev_private;
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@@ -695,6 +696,34 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
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args.v6.ucEncoderMode = encoder_mode;
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args.v6.ucPpll = pll_id;
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break;
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+ case 7:
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+ args.v7.ulPixelClock = cpu_to_le32(clock * 10); /* 100 hz units */
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+ args.v7.ucMiscInfo = 0;
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+ if ((encoder_mode == ATOM_ENCODER_MODE_DVI) &&
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+ (clock > 165000))
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+ args.v7.ucMiscInfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
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+ args.v7.ucCRTC = crtc_id;
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+ if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
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+ switch (bpc) {
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+ case 8:
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+ default:
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+ args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS;
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+ break;
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+ case 10:
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+ args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4;
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+ break;
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+ case 12:
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+ args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2;
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+ break;
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+ case 16:
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+ args.v7.ucDeepColorRatio = PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1;
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+ break;
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+ }
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+ }
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+ args.v7.ucTransmitterID = encoder_id;
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+ args.v7.ucEncoderMode = encoder_mode;
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+ args.v7.ucPpll = pll_id;
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+ break;
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default:
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DRM_ERROR("Unknown table version %d %d\n", frev, crev);
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return;
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