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@@ -0,0 +1,78 @@
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+* APM X-Gene SoC EDAC node
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+
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+EDAC node is defined to describe on-chip error detection and correction.
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+The follow error types are supported:
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+
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+ memory controller - Memory controller
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+ PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
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+
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+The following section describes the EDAC DT node binding.
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+
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+Required properties:
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+- compatible : Shall be "apm,xgene-edac".
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+- regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
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+- regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
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+- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
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+- regmap-efuse : Regmap of the PMD efuse resource.
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+- reg : First resource shall be the CPU bus (PCP) resource.
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+- interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
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+ IRQ(s).
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+
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+Required properties for memory controller subnode:
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+- compatible : Shall be "apm,xgene-edac-mc".
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+- reg : First resource shall be the memory controller unit
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+ (MCU) resource.
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+- memory-controller : Instance number of the memory controller.
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+
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+Required properties for PMD subnode:
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+- compatible : Shall be "apm,xgene-edac-pmd".
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+- reg : First resource shall be the PMD resource.
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+- pmd-controller : Instance number of the PMD controller.
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+
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+Example:
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+ csw: csw@7e200000 {
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+ compatible = "apm,xgene-csw", "syscon";
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+ reg = <0x0 0x7e200000 0x0 0x1000>;
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+ };
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+
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+ mcba: mcba@7e700000 {
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+ compatible = "apm,xgene-mcb", "syscon";
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+ reg = <0x0 0x7e700000 0x0 0x1000>;
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+ };
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+
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+ mcbb: mcbb@7e720000 {
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+ compatible = "apm,xgene-mcb", "syscon";
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+ reg = <0x0 0x7e720000 0x0 0x1000>;
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+ };
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+
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+ efuse: efuse@1054a000 {
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+ compatible = "apm,xgene-efuse", "syscon";
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+ reg = <0x0 0x1054a000 0x0 0x20>;
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+ };
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+
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+ edac@78800000 {
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+ compatible = "apm,xgene-edac";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ regmap-csw = <&csw>;
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+ regmap-mcba = <&mcba>;
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+ regmap-mcbb = <&mcbb>;
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+ regmap-efuse = <&efuse>;
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+ reg = <0x0 0x78800000 0x0 0x100>;
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+ interrupts = <0x0 0x20 0x4>,
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+ <0x0 0x21 0x4>,
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+ <0x0 0x27 0x4>;
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+
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+ edacmc@7e800000 {
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+ compatible = "apm,xgene-edac-mc";
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+ reg = <0x0 0x7e800000 0x0 0x1000>;
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+ memory-controller = <0>;
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+ };
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+
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+ edacpmd@7c000000 {
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+ compatible = "apm,xgene-edac-pmd";
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+ reg = <0x0 0x7c000000 0x0 0x200000>;
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+ pmd-controller = <0>;
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+ };
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+ };
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