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@@ -5116,8 +5116,6 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
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{
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int ret;
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- mutex_lock(&dev_priv->drm.struct_mutex);
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-
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/*
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* We need to fallback to 4K pages since gvt gtt handling doesn't
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* support huge page entries - we will need to check either hypervisor
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@@ -5137,18 +5135,19 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
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dev_priv->gt.cleanup_engine = intel_engine_cleanup;
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}
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+ ret = i915_gem_init_userptr(dev_priv);
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+ if (ret)
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+ return ret;
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+
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/* This is just a security blanket to placate dragons.
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* On some systems, we very sporadically observe that the first TLBs
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* used by the CS may be stale, despite us poking the TLB reset. If
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* we hold the forcewake during initialisation these problems
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* just magically go away.
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*/
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+ mutex_lock(&dev_priv->drm.struct_mutex);
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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- ret = i915_gem_init_userptr(dev_priv);
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- if (ret)
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- goto out_unlock;
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-
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ret = i915_gem_init_ggtt(dev_priv);
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if (ret)
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goto out_unlock;
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