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@@ -410,6 +410,52 @@ retry:
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return rc;
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}
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+static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
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+ unsigned int uhs)
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+{
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+ struct mmc_host *mmc = host->mmc;
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+ u16 ctrl_2;
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+
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+ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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+ /* Select Bus Speed Mode for host */
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+ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
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+ switch (uhs) {
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+ case MMC_TIMING_UHS_SDR12:
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+ ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
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+ break;
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+ case MMC_TIMING_UHS_SDR25:
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+ ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
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+ break;
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+ case MMC_TIMING_UHS_SDR50:
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+ ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
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+ break;
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+ case MMC_TIMING_MMC_HS200:
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+ case MMC_TIMING_UHS_SDR104:
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+ ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
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+ break;
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+ case MMC_TIMING_UHS_DDR50:
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+ case MMC_TIMING_MMC_DDR52:
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+ ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
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+ break;
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+ }
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+
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+ /*
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+ * When clock frequency is less than 100MHz, the feedback clock must be
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+ * provided and DLL must not be used so that tuning can be skipped. To
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+ * provide feedback clock, the mode selection can be any value less
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+ * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
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+ */
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+ if (host->clock <= 100000000 &&
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+ (uhs == MMC_TIMING_MMC_HS400 ||
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+ uhs == MMC_TIMING_MMC_HS200 ||
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+ uhs == MMC_TIMING_UHS_SDR104))
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+ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
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+
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+ dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
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+ mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
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+ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
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+}
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+
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static const struct of_device_id sdhci_msm_dt_match[] = {
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{ .compatible = "qcom,sdhci-msm-v4" },
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{},
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@@ -422,7 +468,7 @@ static const struct sdhci_ops sdhci_msm_ops = {
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.reset = sdhci_reset,
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.set_clock = sdhci_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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- .set_uhs_signaling = sdhci_set_uhs_signaling,
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+ .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
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};
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static const struct sdhci_pltfm_data sdhci_msm_pdata = {
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Ritesh Harjani