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@@ -854,9 +854,8 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
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return true;
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}
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-static bool intel_fbc_can_choose(struct intel_crtc *crtc)
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+static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
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{
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- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_fbc *fbc = &dev_priv->fbc;
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if (intel_vgpu_active(dev_priv)) {
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@@ -874,6 +873,14 @@ static bool intel_fbc_can_choose(struct intel_crtc *crtc)
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return false;
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}
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+ return true;
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+}
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+
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+static bool intel_fbc_can_choose(struct intel_crtc *crtc)
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+{
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+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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+ struct intel_fbc *fbc = &dev_priv->fbc;
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+
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if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A) {
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fbc->no_fbc_reason = "no enabled pipes can have FBC";
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return false;
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@@ -1085,6 +1092,9 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
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if (!fbc_crtc_present && fbc->crtc != NULL)
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goto out;
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+ if (!intel_fbc_can_enable(dev_priv))
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+ goto out;
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+
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/* Simply choose the first CRTC that is compatible and has a visible
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* plane. We could go for fancier schemes such as checking the plane
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* size, but this would just affect the few platforms that don't tie FBC
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