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@@ -1186,10 +1186,12 @@ static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
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dma_cookie_init(&tdc->dma_chan);
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tdc->config_init = false;
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- ret = clk_prepare_enable(tdma->dma_clk);
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+
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+ ret = pm_runtime_get_sync(tdma->dev);
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if (ret < 0)
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- dev_err(tdc2dev(tdc), "clk_prepare_enable failed: %d\n", ret);
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- return ret;
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+ return ret;
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+
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+ return 0;
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}
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static void tegra_dma_free_chan_resources(struct dma_chan *dc)
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@@ -1232,7 +1234,7 @@ static void tegra_dma_free_chan_resources(struct dma_chan *dc)
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list_del(&sg_req->node);
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kfree(sg_req);
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}
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- clk_disable_unprepare(tdma->dma_clk);
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+ pm_runtime_put(tdma->dev);
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tdc->slave_id = 0;
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}
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@@ -1356,20 +1358,14 @@ static int tegra_dma_probe(struct platform_device *pdev)
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spin_lock_init(&tdma->global_lock);
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pm_runtime_enable(&pdev->dev);
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- if (!pm_runtime_enabled(&pdev->dev)) {
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+ if (!pm_runtime_enabled(&pdev->dev))
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ret = tegra_dma_runtime_resume(&pdev->dev);
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- if (ret) {
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- dev_err(&pdev->dev, "dma_runtime_resume failed %d\n",
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- ret);
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- goto err_pm_disable;
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- }
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- }
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+ else
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+ ret = pm_runtime_get_sync(&pdev->dev);
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- /* Enable clock before accessing registers */
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- ret = clk_prepare_enable(tdma->dma_clk);
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if (ret < 0) {
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- dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
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- goto err_pm_disable;
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+ pm_runtime_disable(&pdev->dev);
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+ return ret;
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}
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/* Reset DMA controller */
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@@ -1382,7 +1378,7 @@ static int tegra_dma_probe(struct platform_device *pdev)
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tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
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tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
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- clk_disable_unprepare(tdma->dma_clk);
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+ pm_runtime_put(&pdev->dev);
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INIT_LIST_HEAD(&tdma->dma_dev.channels);
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for (i = 0; i < cdata->nr_channels; i++) {
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@@ -1485,7 +1481,6 @@ err_irq:
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tasklet_kill(&tdc->tasklet);
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}
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-err_pm_disable:
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pm_runtime_disable(&pdev->dev);
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if (!pm_runtime_status_suspended(&pdev->dev))
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tegra_dma_runtime_suspend(&pdev->dev);
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@@ -1543,7 +1538,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
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int ret;
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/* Enable clock before accessing register */
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- ret = tegra_dma_runtime_resume(dev);
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+ ret = pm_runtime_get_sync(dev);
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if (ret < 0)
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return ret;
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@@ -1560,7 +1555,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
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}
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/* Disable clock */
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- tegra_dma_runtime_suspend(dev);
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+ pm_runtime_put(dev);
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return 0;
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}
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@@ -1571,7 +1566,7 @@ static int tegra_dma_pm_resume(struct device *dev)
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int ret;
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/* Enable clock before accessing register */
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- ret = tegra_dma_runtime_resume(dev);
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+ ret = pm_runtime_get_sync(dev);
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if (ret < 0)
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return ret;
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@@ -1592,16 +1587,14 @@ static int tegra_dma_pm_resume(struct device *dev)
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}
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/* Disable clock */
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- tegra_dma_runtime_suspend(dev);
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+ pm_runtime_put(dev);
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return 0;
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}
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#endif
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static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
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-#ifdef CONFIG_PM
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- .runtime_suspend = tegra_dma_runtime_suspend,
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- .runtime_resume = tegra_dma_runtime_resume,
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-#endif
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+ SET_RUNTIME_PM_OPS(tegra_dma_runtime_suspend, tegra_dma_runtime_resume,
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+ NULL)
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SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
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};
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