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@@ -6,7 +6,7 @@ This is the driver for the Altera Triple-Speed Ethernet (TSE) controllers
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using the SGDMA and MSGDMA soft DMA IP components. The driver uses the
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platform bus to obtain component resources. The designs used to test this
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driver were built for a Cyclone(R) V SOC FPGA board, a Cyclone(R) V FPGA board,
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-and tested with ARM and NIOS processor hosts seperately. The anticipated use
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+and tested with ARM and NIOS processor hosts separately. The anticipated use
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cases are simple communications between an embedded system and an external peer
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for status and simple configuration of the embedded system.
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@@ -65,14 +65,14 @@ Driver parameters can be also passed in command line by using:
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4.1) Transmit process
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When the driver's transmit routine is called by the kernel, it sets up a
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transmit descriptor by calling the underlying DMA transmit routine (SGDMA or
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-MSGDMA), and initites a transmit operation. Once the transmit is complete, an
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+MSGDMA), and initiates a transmit operation. Once the transmit is complete, an
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interrupt is driven by the transmit DMA logic. The driver handles the transmit
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completion in the context of the interrupt handling chain by recycling
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resource required to send and track the requested transmit operation.
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4.2) Receive process
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The driver will post receive buffers to the receive DMA logic during driver
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-intialization. Receive buffers may or may not be queued depending upon the
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+initialization. Receive buffers may or may not be queued depending upon the
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underlying DMA logic (MSGDMA is able queue receive buffers, SGDMA is not able
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to queue receive buffers to the SGDMA receive logic). When a packet is
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received, the DMA logic generates an interrupt. The driver handles a receive
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