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@@ -117,8 +117,6 @@
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#define UARTSFIFO_TXOF 0x02
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#define UARTSFIFO_RXUF 0x01
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-#define DMA_MAXBURST 16
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-#define DMA_MAXBURST_MASK (DMA_MAXBURST - 1)
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#define FSL_UART_RX_DMA_BUFFER_SIZE 64
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#define DRIVER_NAME "fsl-lpuart"
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@@ -236,7 +234,7 @@ static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count)
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dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus,
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UART_XMIT_SIZE, DMA_TO_DEVICE);
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- sport->dma_tx_bytes = count & ~(DMA_MAXBURST_MASK);
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+ sport->dma_tx_bytes = count & ~(sport->txfifo_size - 1);
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tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail;
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sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan,
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tx_bus_addr, sport->dma_tx_bytes,
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@@ -265,7 +263,7 @@ static void lpuart_prepare_tx(struct lpuart_port *sport)
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if (!count)
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return;
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- if (count < DMA_MAXBURST)
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+ if (count < sport->txfifo_size)
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writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,
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sport->port.membase + UARTCR5);
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else {
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@@ -595,15 +593,7 @@ static void lpuart_setup_watermark(struct lpuart_port *sport)
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UARTCR2_RIE | UARTCR2_RE);
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writeb(cr2, sport->port.membase + UARTCR2);
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- /* determine FIFO size and enable FIFO mode */
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val = readb(sport->port.membase + UARTPFIFO);
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-
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- sport->txfifo_size = 0x1 << (((val >> UARTPFIFO_TXSIZE_OFF) &
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- UARTPFIFO_FIFOSIZE_MASK) + 1);
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-
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- sport->rxfifo_size = 0x1 << (((val >> UARTPFIFO_RXSIZE_OFF) &
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- UARTPFIFO_FIFOSIZE_MASK) + 1);
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-
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writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
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sport->port.membase + UARTPFIFO);
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@@ -648,7 +638,7 @@ static int lpuart_dma_tx_request(struct uart_port *port)
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dma_buf = sport->port.state->xmit.buf;
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dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
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dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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- dma_tx_sconfig.dst_maxburst = DMA_MAXBURST;
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+ dma_tx_sconfig.dst_maxburst = sport->txfifo_size;
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dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
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ret = dmaengine_slave_config(tx_chan, &dma_tx_sconfig);
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@@ -761,7 +751,16 @@ static int lpuart_startup(struct uart_port *port)
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unsigned long flags;
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unsigned char temp;
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- /*whether use dma support by dma request results*/
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+ /* determine FIFO size and enable FIFO mode */
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+ temp = readb(sport->port.membase + UARTPFIFO);
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+
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+ sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &
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+ UARTPFIFO_FIFOSIZE_MASK) + 1);
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+
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+ sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &
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+ UARTPFIFO_FIFOSIZE_MASK) + 1);
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+
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+ /* Whether use dma support by dma request results */
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if (lpuart_dma_tx_request(port) || lpuart_dma_rx_request(port)) {
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sport->lpuart_dma_use = false;
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} else {
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