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@@ -9,18 +9,18 @@
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#define DCON_REG_ID 0
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#define DCON_REG_MODE 1
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-#define MODE_PASSTHRU (1<<0)
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-#define MODE_SLEEP (1<<1)
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-#define MODE_SLEEP_AUTO (1<<2)
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-#define MODE_BL_ENABLE (1<<3)
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-#define MODE_BLANK (1<<4)
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-#define MODE_CSWIZZLE (1<<5)
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-#define MODE_COL_AA (1<<6)
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-#define MODE_MONO_LUMA (1<<7)
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-#define MODE_SCAN_INT (1<<8)
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-#define MODE_CLOCKDIV (1<<9)
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-#define MODE_DEBUG (1<<14)
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-#define MODE_SELFTEST (1<<15)
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+#define MODE_PASSTHRU bit(0)
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+#define MODE_SLEEP bit(1)
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+#define MODE_SLEEP_AUTO bit(2)
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+#define MODE_BL_ENABLE bit(3)
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+#define MODE_BLANK bit(4)
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+#define MODE_CSWIZZLE bit(5)
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+#define MODE_COL_AA bit(6)
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+#define MODE_MONO_LUMA bit(7)
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+#define MODE_SCAN_INT bit(8)
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+#define MODE_CLOCKDIV bit(9)
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+#define MODE_DEBUG bit(14)
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+#define MODE_SELFTEST bit(15)
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#define DCON_REG_HRES 0x2
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#define DCON_REG_HTOTAL 0x3
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@@ -35,11 +35,11 @@
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#define DCON_REG_MEM_OPT_B 0x42
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/* Load Delay Locked Loop (DLL) settings for clock delay */
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-#define MEM_DLL_CLOCK_DELAY (1<<0)
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+#define MEM_DLL_CLOCK_DELAY bit(0)
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/* Memory controller power down function */
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-#define MEM_POWER_DOWN (1<<8)
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+#define MEM_POWER_DOWN bit(8)
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/* Memory controller software reset */
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-#define MEM_SOFT_RESET (1<<0)
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+#define MEM_SOFT_RESET bit(0)
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/* Status values */
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