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@@ -33,6 +33,7 @@
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/* Extended Registers */
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#define DP83867_RGMIICTL 0x0032
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#define DP83867_RGMIIDCTL 0x0086
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+#define DP83867_IO_MUX_CFG 0x0170
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#define DP83867_SW_RESET BIT(15)
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#define DP83867_SW_RESTART BIT(14)
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@@ -62,10 +63,17 @@
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/* RGMIIDCTL bits */
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#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
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+/* IO_MUX_CFG bits */
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+#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
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+
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+#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
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+#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
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+
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struct dp83867_private {
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int rx_id_delay;
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int tx_id_delay;
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int fifo_depth;
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+ int io_impedance;
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};
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static int dp83867_ack_interrupt(struct phy_device *phydev)
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@@ -111,6 +119,14 @@ static int dp83867_of_init(struct phy_device *phydev)
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if (!of_node)
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return -ENODEV;
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+ dp83867->io_impedance = -EINVAL;
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+
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+ /* Optional configuration */
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+ if (of_property_read_bool(of_node, "ti,max-output-impedance"))
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+ dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
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+ else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
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+ dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
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+
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ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
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&dp83867->rx_id_delay);
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if (ret)
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@@ -184,6 +200,18 @@ static int dp83867_config_init(struct phy_device *phydev)
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phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
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DP83867_DEVADDR, delay);
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+
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+ if (dp83867->io_impedance >= 0) {
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+ val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
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+ DP83867_DEVADDR);
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+
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+ val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
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+ val |= dp83867->io_impedance &
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+ DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
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+
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+ phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
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+ DP83867_DEVADDR, val);
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+ }
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}
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return 0;
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