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@@ -0,0 +1,535 @@
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+/*
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+ * Synopsys DDR ECC Driver
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+ * This driver is based on ppc4xx_edac.c drivers
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+ *
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+ * Copyright (C) 2012 - 2014 Xilinx, Inc.
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+ *
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+ * This program is free software: you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation, either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details
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+ */
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+
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+#include <linux/edac.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+
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+#include "edac_core.h"
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+
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+/* Number of cs_rows needed per memory controller */
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+#define SYNPS_EDAC_NR_CSROWS 1
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+
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+/* Number of channels per memory controller */
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+#define SYNPS_EDAC_NR_CHANS 1
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+
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+/* Granularity of reported error in bytes */
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+#define SYNPS_EDAC_ERR_GRAIN 1
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+
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+#define SYNPS_EDAC_MSG_SIZE 256
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+
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+#define SYNPS_EDAC_MOD_STRING "synps_edac"
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+#define SYNPS_EDAC_MOD_VER "1"
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+
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+/* Synopsys DDR memory controller registers that are relevant to ECC */
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+#define CTRL_OFST 0x0
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+#define T_ZQ_OFST 0xA4
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+
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+/* ECC control register */
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+#define ECC_CTRL_OFST 0xC4
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+/* ECC log register */
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+#define CE_LOG_OFST 0xC8
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+/* ECC address register */
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+#define CE_ADDR_OFST 0xCC
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+/* ECC data[31:0] register */
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+#define CE_DATA_31_0_OFST 0xD0
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+
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+/* Uncorrectable error info registers */
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+#define UE_LOG_OFST 0xDC
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+#define UE_ADDR_OFST 0xE0
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+#define UE_DATA_31_0_OFST 0xE4
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+
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+#define STAT_OFST 0xF0
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+#define SCRUB_OFST 0xF4
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+
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+/* Control register bit field definitions */
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+#define CTRL_BW_MASK 0xC
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+#define CTRL_BW_SHIFT 2
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+
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+#define DDRCTL_WDTH_16 1
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+#define DDRCTL_WDTH_32 0
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+
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+/* ZQ register bit field definitions */
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+#define T_ZQ_DDRMODE_MASK 0x2
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+
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+/* ECC control register bit field definitions */
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+#define ECC_CTRL_CLR_CE_ERR 0x2
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+#define ECC_CTRL_CLR_UE_ERR 0x1
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+
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+/* ECC correctable/uncorrectable error log register definitions */
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+#define LOG_VALID 0x1
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+#define CE_LOG_BITPOS_MASK 0xFE
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+#define CE_LOG_BITPOS_SHIFT 1
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+
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+/* ECC correctable/uncorrectable error address register definitions */
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+#define ADDR_COL_MASK 0xFFF
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+#define ADDR_ROW_MASK 0xFFFF000
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+#define ADDR_ROW_SHIFT 12
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+#define ADDR_BANK_MASK 0x70000000
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+#define ADDR_BANK_SHIFT 28
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+
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+/* ECC statistic register definitions */
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+#define STAT_UECNT_MASK 0xFF
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+#define STAT_CECNT_MASK 0xFF00
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+#define STAT_CECNT_SHIFT 8
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+
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+/* ECC scrub register definitions */
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+#define SCRUB_MODE_MASK 0x7
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+#define SCRUB_MODE_SECDED 0x4
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+
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+/**
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+ * struct ecc_error_info - ECC error log information
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+ * @row: Row number
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+ * @col: Column number
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+ * @bank: Bank number
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+ * @bitpos: Bit position
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+ * @data: Data causing the error
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+ */
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+struct ecc_error_info {
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+ u32 row;
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+ u32 col;
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+ u32 bank;
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+ u32 bitpos;
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+ u32 data;
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+};
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+
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+/**
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+ * struct synps_ecc_status - ECC status information to report
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+ * @ce_cnt: Correctable error count
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+ * @ue_cnt: Uncorrectable error count
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+ * @ceinfo: Correctable error log information
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+ * @ueinfo: Uncorrectable error log information
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+ */
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+struct synps_ecc_status {
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+ u32 ce_cnt;
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+ u32 ue_cnt;
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+ struct ecc_error_info ceinfo;
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+ struct ecc_error_info ueinfo;
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+};
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+
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+/**
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+ * struct synps_edac_priv - DDR memory controller private instance data
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+ * @baseaddr: Base address of the DDR controller
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+ * @message: Buffer for framing the event specific info
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+ * @stat: ECC status information
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+ * @ce_cnt: Correctable Error count
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+ * @ue_cnt: Uncorrectable Error count
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+ */
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+struct synps_edac_priv {
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+ void __iomem *baseaddr;
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+ char message[SYNPS_EDAC_MSG_SIZE];
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+ struct synps_ecc_status stat;
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+ u32 ce_cnt;
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+ u32 ue_cnt;
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+};
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+
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+/**
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+ * synps_edac_geterror_info - Get the current ecc error info
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+ * @base: Pointer to the base address of the ddr memory controller
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+ * @p: Pointer to the synopsys ecc status structure
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+ *
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+ * Determines there is any ecc error or not
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+ *
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+ * Return: one if there is no error otherwise returns zero
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+ */
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+static int synps_edac_geterror_info(void __iomem *base,
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+ struct synps_ecc_status *p)
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+{
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+ u32 regval, clearval = 0;
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+
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+ regval = readl(base + STAT_OFST);
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+ if (!regval)
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+ return 1;
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+
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+ p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT;
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+ p->ue_cnt = regval & STAT_UECNT_MASK;
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+
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+ regval = readl(base + CE_LOG_OFST);
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+ if (!(p->ce_cnt && (regval & LOG_VALID)))
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+ goto ue_err;
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+
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+ p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT;
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+ regval = readl(base + CE_ADDR_OFST);
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+ p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;
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+ p->ceinfo.col = regval & ADDR_COL_MASK;
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+ p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;
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+ p->ceinfo.data = readl(base + CE_DATA_31_0_OFST);
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+ edac_dbg(3, "ce bit position: %d data: %d\n", p->ceinfo.bitpos,
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+ p->ceinfo.data);
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+ clearval = ECC_CTRL_CLR_CE_ERR;
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+
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+ue_err:
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+ regval = readl(base + UE_LOG_OFST);
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+ if (!(p->ue_cnt && (regval & LOG_VALID)))
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+ goto out;
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+
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+ regval = readl(base + UE_ADDR_OFST);
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+ p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;
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+ p->ueinfo.col = regval & ADDR_COL_MASK;
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+ p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;
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+ p->ueinfo.data = readl(base + UE_DATA_31_0_OFST);
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+ clearval |= ECC_CTRL_CLR_UE_ERR;
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+
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+out:
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+ writel(clearval, base + ECC_CTRL_OFST);
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+ writel(0x0, base + ECC_CTRL_OFST);
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+
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+ return 0;
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+}
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+
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+/**
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+ * synps_edac_handle_error - Handle controller error types CE and UE
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+ * @mci: Pointer to the edac memory controller instance
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+ * @p: Pointer to the synopsys ecc status structure
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+ *
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+ * Handles the controller ECC correctable and un correctable error.
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+ */
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+static void synps_edac_handle_error(struct mem_ctl_info *mci,
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+ struct synps_ecc_status *p)
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+{
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+ struct synps_edac_priv *priv = mci->pvt_info;
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+ struct ecc_error_info *pinf;
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+
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+ if (p->ce_cnt) {
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+ pinf = &p->ceinfo;
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+ snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
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+ "DDR ECC error type :%s Row %d Bank %d Col %d ",
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+ "CE", pinf->row, pinf->bank, pinf->col);
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+ edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
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+ p->ce_cnt, 0, 0, 0, 0, 0, -1,
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+ priv->message, "");
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+ }
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+
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+ if (p->ue_cnt) {
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+ pinf = &p->ueinfo;
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+ snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
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+ "DDR ECC error type :%s Row %d Bank %d Col %d ",
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+ "UE", pinf->row, pinf->bank, pinf->col);
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+ edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
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+ p->ue_cnt, 0, 0, 0, 0, 0, -1,
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+ priv->message, "");
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+ }
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+
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+ memset(p, 0, sizeof(*p));
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+}
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+
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+/**
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+ * synps_edac_check - Check controller for ECC errors
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+ * @mci: Pointer to the edac memory controller instance
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+ *
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+ * Used to check and post ECC errors. Called by the polling thread
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+ */
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+static void synps_edac_check(struct mem_ctl_info *mci)
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+{
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+ struct synps_edac_priv *priv = mci->pvt_info;
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+ int status;
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+
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+ status = synps_edac_geterror_info(priv->baseaddr, &priv->stat);
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+ if (status)
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+ return;
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+
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+ priv->ce_cnt += priv->stat.ce_cnt;
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+ priv->ue_cnt += priv->stat.ue_cnt;
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+ synps_edac_handle_error(mci, &priv->stat);
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+
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+ edac_dbg(3, "Total error count ce %d ue %d\n",
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+ priv->ce_cnt, priv->ue_cnt);
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+}
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+
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+/**
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+ * synps_edac_get_dtype - Return the controller memory width
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+ * @base: Pointer to the ddr memory controller base address
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+ *
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+ * Get the EDAC device type width appropriate for the current controller
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+ * configuration.
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+ *
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+ * Return: a device type width enumeration.
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+ */
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+static enum dev_type synps_edac_get_dtype(const void __iomem *base)
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+{
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+ enum dev_type dt;
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+ u32 width;
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+
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+ width = readl(base + CTRL_OFST);
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+ width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT;
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+
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+ switch (width) {
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+ case DDRCTL_WDTH_16:
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+ dt = DEV_X2;
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+ break;
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+ case DDRCTL_WDTH_32:
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+ dt = DEV_X4;
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+ break;
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+ default:
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+ dt = DEV_UNKNOWN;
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+ }
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+
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+ return dt;
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+}
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+
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+/**
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+ * synps_edac_get_eccstate - Return the controller ecc enable/disable status
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+ * @base: Pointer to the ddr memory controller base address
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+ *
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+ * Get the ECC enable/disable status for the controller
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+ *
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+ * Return: a ecc status boolean i.e true/false - enabled/disabled.
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+ */
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+static bool synps_edac_get_eccstate(void __iomem *base)
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+{
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+ enum dev_type dt;
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+ u32 ecctype;
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+ bool state = false;
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+
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+ dt = synps_edac_get_dtype(base);
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+ if (dt == DEV_UNKNOWN)
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+ return state;
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+
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+ ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK;
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+ if ((ecctype == SCRUB_MODE_SECDED) && (dt == DEV_X2))
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+ state = true;
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+
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+ return state;
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+}
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+
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+/**
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+ * synps_edac_get_memsize - reads the size of the attached memory device
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+ *
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+ * Return: the memory size in bytes
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+ */
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+static u32 synps_edac_get_memsize(void)
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+{
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+ struct sysinfo inf;
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+
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+ si_meminfo(&inf);
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+
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+ return inf.totalram * inf.mem_unit;
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+}
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+
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+/**
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+ * synps_edac_get_mtype - Returns controller memory type
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+ * @base: pointer to the synopsys ecc status structure
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+ *
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+ * Get the EDAC memory type appropriate for the current controller
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+ * configuration.
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+ *
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+ * Return: a memory type enumeration.
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+ */
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+static enum mem_type synps_edac_get_mtype(const void __iomem *base)
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+{
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+ enum mem_type mt;
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+ u32 memtype;
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+
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+ memtype = readl(base + T_ZQ_OFST);
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+
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+ if (memtype & T_ZQ_DDRMODE_MASK)
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+ mt = MEM_DDR3;
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+ else
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+ mt = MEM_DDR2;
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+
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+ return mt;
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+}
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+
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+/**
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+ * synps_edac_init_csrows - Initialize the cs row data
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+ * @mci: Pointer to the edac memory controller instance
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+ *
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+ * Initializes the chip select rows associated with the EDAC memory
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+ * controller instance
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+ *
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+ * Return: Unconditionally 0.
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+ */
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+static int synps_edac_init_csrows(struct mem_ctl_info *mci)
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+{
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+ struct csrow_info *csi;
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+ struct dimm_info *dimm;
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+ struct synps_edac_priv *priv = mci->pvt_info;
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+ u32 size;
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+ int row, j;
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+
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+ for (row = 0; row < mci->nr_csrows; row++) {
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+ csi = mci->csrows[row];
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+ size = synps_edac_get_memsize();
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+
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+ for (j = 0; j < csi->nr_channels; j++) {
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+ dimm = csi->channels[j]->dimm;
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+ dimm->edac_mode = EDAC_FLAG_SECDED;
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+ dimm->mtype = synps_edac_get_mtype(priv->baseaddr);
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+ dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels;
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+ dimm->grain = SYNPS_EDAC_ERR_GRAIN;
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+ dimm->dtype = synps_edac_get_dtype(priv->baseaddr);
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+/**
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+ * synps_edac_mc_init - Initialize driver instance
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+ * @mci: Pointer to the edac memory controller instance
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+ * @pdev: Pointer to the platform_device struct
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+ *
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+ * Performs initialization of the EDAC memory controller instance and
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+ * related driver-private data associated with the memory controller the
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+ * instance is bound to.
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+ *
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+ * Return: Always zero.
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+ */
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+static int synps_edac_mc_init(struct mem_ctl_info *mci,
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+ struct platform_device *pdev)
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+{
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+ int status;
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+ struct synps_edac_priv *priv;
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+
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+ mci->pdev = &pdev->dev;
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+ priv = mci->pvt_info;
|
|
|
+ platform_set_drvdata(pdev, mci);
|
|
|
+
|
|
|
+ /* Initialize controller capabilities and configuration */
|
|
|
+ mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2;
|
|
|
+ mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
|
|
|
+ mci->scrub_cap = SCRUB_HW_SRC;
|
|
|
+ mci->scrub_mode = SCRUB_NONE;
|
|
|
+
|
|
|
+ mci->edac_cap = EDAC_FLAG_SECDED;
|
|
|
+ mci->ctl_name = "synps_ddr_controller";
|
|
|
+ mci->dev_name = SYNPS_EDAC_MOD_STRING;
|
|
|
+ mci->mod_name = SYNPS_EDAC_MOD_VER;
|
|
|
+ mci->mod_ver = "1";
|
|
|
+
|
|
|
+ edac_op_state = EDAC_OPSTATE_POLL;
|
|
|
+ mci->edac_check = synps_edac_check;
|
|
|
+ mci->ctl_page_to_phys = NULL;
|
|
|
+
|
|
|
+ status = synps_edac_init_csrows(mci);
|
|
|
+
|
|
|
+ return status;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * synps_edac_mc_probe - Check controller and bind driver
|
|
|
+ * @pdev: Pointer to the platform_device struct
|
|
|
+ *
|
|
|
+ * Probes a specific controller instance for binding with the driver.
|
|
|
+ *
|
|
|
+ * Return: 0 if the controller instance was successfully bound to the
|
|
|
+ * driver; otherwise, < 0 on error.
|
|
|
+ */
|
|
|
+static int synps_edac_mc_probe(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct mem_ctl_info *mci;
|
|
|
+ struct edac_mc_layer layers[2];
|
|
|
+ struct synps_edac_priv *priv;
|
|
|
+ int rc;
|
|
|
+ struct resource *res;
|
|
|
+ void __iomem *baseaddr;
|
|
|
+
|
|
|
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
+ baseaddr = devm_ioremap_resource(&pdev->dev, res);
|
|
|
+ if (IS_ERR(baseaddr))
|
|
|
+ return PTR_ERR(baseaddr);
|
|
|
+
|
|
|
+ if (!synps_edac_get_eccstate(baseaddr)) {
|
|
|
+ edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n");
|
|
|
+ return -ENXIO;
|
|
|
+ }
|
|
|
+
|
|
|
+ layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
|
|
|
+ layers[0].size = SYNPS_EDAC_NR_CSROWS;
|
|
|
+ layers[0].is_virt_csrow = true;
|
|
|
+ layers[1].type = EDAC_MC_LAYER_CHANNEL;
|
|
|
+ layers[1].size = SYNPS_EDAC_NR_CHANS;
|
|
|
+ layers[1].is_virt_csrow = false;
|
|
|
+
|
|
|
+ mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
|
|
|
+ sizeof(struct synps_edac_priv));
|
|
|
+ if (!mci) {
|
|
|
+ edac_printk(KERN_ERR, EDAC_MC,
|
|
|
+ "Failed memory allocation for mc instance\n");
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+
|
|
|
+ priv = mci->pvt_info;
|
|
|
+ priv->baseaddr = baseaddr;
|
|
|
+ rc = synps_edac_mc_init(mci, pdev);
|
|
|
+ if (rc) {
|
|
|
+ edac_printk(KERN_ERR, EDAC_MC,
|
|
|
+ "Failed to initialize instance\n");
|
|
|
+ goto free_edac_mc;
|
|
|
+ }
|
|
|
+
|
|
|
+ rc = edac_mc_add_mc(mci);
|
|
|
+ if (rc) {
|
|
|
+ edac_printk(KERN_ERR, EDAC_MC,
|
|
|
+ "Failed to register with EDAC core\n");
|
|
|
+ goto free_edac_mc;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Start capturing the correctable and uncorrectable errors. A write of
|
|
|
+ * 0 starts the counters.
|
|
|
+ */
|
|
|
+ writel(0x0, baseaddr + ECC_CTRL_OFST);
|
|
|
+ return rc;
|
|
|
+
|
|
|
+free_edac_mc:
|
|
|
+ edac_mc_free(mci);
|
|
|
+
|
|
|
+ return rc;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * synps_edac_mc_remove - Unbind driver from controller
|
|
|
+ * @pdev: Pointer to the platform_device struct
|
|
|
+ *
|
|
|
+ * Return: Unconditionally 0
|
|
|
+ */
|
|
|
+static int synps_edac_mc_remove(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct mem_ctl_info *mci = platform_get_drvdata(pdev);
|
|
|
+
|
|
|
+ edac_mc_del_mc(&pdev->dev);
|
|
|
+ edac_mc_free(mci);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static struct of_device_id synps_edac_match[] = {
|
|
|
+ { .compatible = "xlnx,zynq-ddrc-a05", },
|
|
|
+ { /* end of table */ }
|
|
|
+};
|
|
|
+
|
|
|
+MODULE_DEVICE_TABLE(of, synps_edac_match);
|
|
|
+
|
|
|
+static struct platform_driver synps_edac_mc_driver = {
|
|
|
+ .driver = {
|
|
|
+ .name = "synopsys-edac",
|
|
|
+ .of_match_table = synps_edac_match,
|
|
|
+ },
|
|
|
+ .probe = synps_edac_mc_probe,
|
|
|
+ .remove = synps_edac_mc_remove,
|
|
|
+};
|
|
|
+
|
|
|
+module_platform_driver(synps_edac_mc_driver);
|
|
|
+
|
|
|
+MODULE_AUTHOR("Xilinx Inc");
|
|
|
+MODULE_DESCRIPTION("Synopsys DDR ECC driver");
|
|
|
+MODULE_LICENSE("GPL v2");
|
Linus Torvalds