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@@ -0,0 +1,31 @@
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+Allwinner Display Engine 2.0 Clock Control Binding
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+--------------------------------------------------
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+
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+Required properties :
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+- compatible: must contain one of the following compatibles:
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+ - "allwinner,sun8i-a83t-de2-clk"
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+ - "allwinner,sun8i-v3s-de2-clk"
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+ - "allwinner,sun50i-h5-de2-clk"
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+
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+- reg: Must contain the registers base address and length
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+- clocks: phandle to the clocks feeding the display engine subsystem.
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+ Three are needed:
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+ - "mod": the display engine module clock
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+ - "bus": the bus clock for the whole display engine subsystem
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+- clock-names: Must contain the clock names described just above
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+- resets: phandle to the reset control for the display engine subsystem.
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+- #clock-cells : must contain 1
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+- #reset-cells : must contain 1
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+
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+Example:
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+de2_clocks: clock@1000000 {
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+ compatible = "allwinner,sun8i-a83t-de2-clk";
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+ reg = <0x01000000 0x100000>;
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+ clocks = <&ccu CLK_BUS_DE>,
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+ <&ccu CLK_DE>;
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+ clock-names = "bus",
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+ "mod";
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+ resets = <&ccu RST_BUS_DE>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+};
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