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@@ -2915,7 +2915,7 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
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{
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u32 timing_h, timing_v, l;
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- bool onoff, rf, ipc;
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+ bool onoff, rf, ipc, vs, hs, de;
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timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
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FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
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@@ -2927,6 +2927,39 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
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dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
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dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
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+ switch (vsync_level) {
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+ case OMAPDSS_SIG_ACTIVE_LOW:
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+ vs = true;
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+ break;
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+ case OMAPDSS_SIG_ACTIVE_HIGH:
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+ vs = false;
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+ break;
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+ default:
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+ BUG();
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+ }
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+
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+ switch (hsync_level) {
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+ case OMAPDSS_SIG_ACTIVE_LOW:
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+ hs = true;
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+ break;
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+ case OMAPDSS_SIG_ACTIVE_HIGH:
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+ hs = false;
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+ break;
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+ default:
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+ BUG();
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+ }
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+
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+ switch (de_level) {
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+ case OMAPDSS_SIG_ACTIVE_LOW:
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+ de = true;
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+ break;
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+ case OMAPDSS_SIG_ACTIVE_HIGH:
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+ de = false;
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+ break;
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+ default:
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+ BUG();
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+ }
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+
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switch (data_pclk_edge) {
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case OMAPDSS_DRIVE_SIG_RISING_EDGE:
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ipc = false;
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@@ -2954,10 +2987,10 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
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l = FLD_VAL(onoff, 17, 17) |
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FLD_VAL(rf, 16, 16) |
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- FLD_VAL(de_level, 15, 15) |
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+ FLD_VAL(de, 15, 15) |
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FLD_VAL(ipc, 14, 14) |
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- FLD_VAL(hsync_level, 13, 13) |
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- FLD_VAL(vsync_level, 12, 12);
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+ FLD_VAL(hs, 13, 13) |
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+ FLD_VAL(vs, 12, 12);
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dispc_write_reg(DISPC_POL_FREQ(channel), l);
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