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@@ -41,13 +41,7 @@
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#define DRIVER_NAME "i2c-designware-pci"
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#define DRIVER_NAME "i2c-designware-pci"
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enum dw_pci_ctl_id_t {
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enum dw_pci_ctl_id_t {
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- medfield_0,
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- medfield_1,
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- medfield_2,
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- medfield_3,
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- medfield_4,
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- medfield_5,
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-
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+ medfield,
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baytrail,
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baytrail,
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haswell,
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haswell,
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};
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};
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@@ -68,6 +62,7 @@ struct dw_pci_controller {
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u32 clk_khz;
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u32 clk_khz;
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u32 functionality;
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u32 functionality;
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struct dw_scl_sda_cfg *scl_sda_cfg;
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struct dw_scl_sda_cfg *scl_sda_cfg;
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+ int (*setup)(struct pci_dev *pdev, struct dw_pci_controller *c);
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};
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};
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#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \
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#define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \
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@@ -98,48 +93,33 @@ static struct dw_scl_sda_cfg hsw_config = {
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.sda_hold = 0x9,
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.sda_hold = 0x9,
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};
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};
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+static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
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+{
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+ switch (pdev->device) {
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+ case 0x0817:
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+ c->bus_cfg &= ~DW_IC_CON_SPEED_MASK;
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+ c->bus_cfg |= DW_IC_CON_SPEED_STD;
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+ case 0x0818:
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+ case 0x0819:
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+ c->bus_num = pdev->device - 0x817 + 3;
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+ return 0;
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+ case 0x082C:
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+ case 0x082D:
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+ case 0x082E:
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+ c->bus_num = pdev->device - 0x82C + 0;
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+ return 0;
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+ }
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+ return -ENODEV;
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+}
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+
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static struct dw_pci_controller dw_pci_controllers[] = {
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static struct dw_pci_controller dw_pci_controllers[] = {
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- [medfield_0] = {
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- .bus_num = 0,
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- .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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- .tx_fifo_depth = 32,
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- .rx_fifo_depth = 32,
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- .clk_khz = 25000,
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- },
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- [medfield_1] = {
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- .bus_num = 1,
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- .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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- .tx_fifo_depth = 32,
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- .rx_fifo_depth = 32,
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- .clk_khz = 25000,
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- },
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- [medfield_2] = {
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- .bus_num = 2,
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- .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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- .tx_fifo_depth = 32,
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- .rx_fifo_depth = 32,
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- .clk_khz = 25000,
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- },
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- [medfield_3] = {
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- .bus_num = 3,
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- .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
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- .tx_fifo_depth = 32,
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- .rx_fifo_depth = 32,
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- .clk_khz = 25000,
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- },
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- [medfield_4] = {
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- .bus_num = 4,
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- .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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- .tx_fifo_depth = 32,
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- .rx_fifo_depth = 32,
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- .clk_khz = 25000,
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- },
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- [medfield_5] = {
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- .bus_num = 5,
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+ [medfield] = {
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+ .bus_num = -1,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
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.tx_fifo_depth = 32,
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.tx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.rx_fifo_depth = 32,
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.clk_khz = 25000,
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.clk_khz = 25000,
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+ .setup = mfld_setup,
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},
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},
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[baytrail] = {
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[baytrail] = {
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.bus_num = -1,
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.bus_num = -1,
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@@ -224,6 +204,13 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev,
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dev->base = pcim_iomap_table(pdev)[0];
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dev->base = pcim_iomap_table(pdev)[0];
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dev->dev = &pdev->dev;
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dev->dev = &pdev->dev;
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dev->irq = pdev->irq;
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dev->irq = pdev->irq;
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+
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+ if (controller->setup) {
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+ r = controller->setup(pdev, controller);
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+ if (r)
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+ return r;
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+ }
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+
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dev->functionality = controller->functionality |
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dev->functionality = controller->functionality |
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DW_DEFAULT_FUNCTIONALITY;
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DW_DEFAULT_FUNCTIONALITY;
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@@ -276,12 +263,12 @@ MODULE_ALIAS("i2c_designware-pci");
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static const struct pci_device_id i2_designware_pci_ids[] = {
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static const struct pci_device_id i2_designware_pci_ids[] = {
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/* Medfield */
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/* Medfield */
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- { PCI_VDEVICE(INTEL, 0x0817), medfield_3 },
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- { PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
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- { PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
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- { PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
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- { PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
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- { PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
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+ { PCI_VDEVICE(INTEL, 0x0817), medfield },
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+ { PCI_VDEVICE(INTEL, 0x0818), medfield },
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+ { PCI_VDEVICE(INTEL, 0x0819), medfield },
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+ { PCI_VDEVICE(INTEL, 0x082C), medfield },
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+ { PCI_VDEVICE(INTEL, 0x082D), medfield },
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+ { PCI_VDEVICE(INTEL, 0x082E), medfield },
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/* Baytrail */
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/* Baytrail */
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{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
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{ PCI_VDEVICE(INTEL, 0x0F41), baytrail },
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{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
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{ PCI_VDEVICE(INTEL, 0x0F42), baytrail },
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