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@@ -1819,6 +1819,22 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
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adev->gfx.config.backend_enable_mask,
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num_rb_pipes);
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}
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+
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+ /* cache the values for userspace */
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+ for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
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+ for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
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+ gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff);
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+ adev->gfx.config.rb_config[i][j].rb_backend_disable =
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+ RREG32(mmCC_RB_BACKEND_DISABLE);
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+ adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
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+ RREG32(mmGC_USER_RB_BACKEND_DISABLE);
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+ adev->gfx.config.rb_config[i][j].raster_config =
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+ RREG32(mmPA_SC_RASTER_CONFIG);
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+ adev->gfx.config.rb_config[i][j].raster_config_1 =
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+ RREG32(mmPA_SC_RASTER_CONFIG_1);
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+ }
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+ }
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+ gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
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mutex_unlock(&adev->grbm_idx_mutex);
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}
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