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@@ -44,8 +44,8 @@
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#include <asm/hardware/cache-l2x0.h>
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/* SCIF */
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-#define SCIF_INFO(baseaddr, irq) \
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-{ \
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+#define R8A7778_SCIF(index, baseaddr, irq) \
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+static struct plat_sci_port scif##index##_platform_data = { \
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.mapbase = baseaddr, \
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
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@@ -54,14 +54,17 @@
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.irqs = SCIx_IRQ_MUXED(irq), \
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}
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-static struct plat_sci_port scif_platform_data[] __initdata = {
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- SCIF_INFO(0xffe40000, gic_iid(0x66)),
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- SCIF_INFO(0xffe41000, gic_iid(0x67)),
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- SCIF_INFO(0xffe42000, gic_iid(0x68)),
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- SCIF_INFO(0xffe43000, gic_iid(0x69)),
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- SCIF_INFO(0xffe44000, gic_iid(0x6a)),
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- SCIF_INFO(0xffe45000, gic_iid(0x6b)),
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-};
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+R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
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+R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
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+R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
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+R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
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+R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
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+R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
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+
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+#define r8a7778_register_scif(index) \
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+ platform_device_register_data(&platform_bus, "sh-sci", index, \
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+ &scif##index##_platform_data, \
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+ sizeof(scif##index##_platform_data))
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/* TMU */
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static struct resource sh_tmu0_resources[] __initdata = {
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@@ -287,8 +290,6 @@ static void __init r8a7778_register_hspi(int id)
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void __init r8a7778_add_dt_devices(void)
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{
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- int i;
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-
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
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if (base) {
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@@ -300,11 +301,12 @@ void __init r8a7778_add_dt_devices(void)
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}
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#endif
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- for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
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- platform_device_register_data(&platform_bus, "sh-sci", i,
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- &scif_platform_data[i],
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- sizeof(struct plat_sci_port));
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-
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+ r8a7778_register_scif(0);
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+ r8a7778_register_scif(1);
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+ r8a7778_register_scif(2);
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+ r8a7778_register_scif(3);
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+ r8a7778_register_scif(4);
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+ r8a7778_register_scif(5);
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r8a7778_register_tmu(0);
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r8a7778_register_tmu(1);
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}
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