|
@@ -552,11 +552,15 @@ static int hns_roce_v2_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
|
|
|
}
|
|
|
|
|
|
/* rq support inline data */
|
|
|
- sge_list = hr_qp->rq_inl_buf.wqe_list[ind].sg_list;
|
|
|
- hr_qp->rq_inl_buf.wqe_list[ind].sge_cnt = (u32)wr->num_sge;
|
|
|
- for (i = 0; i < wr->num_sge; i++) {
|
|
|
- sge_list[i].addr = (void *)(u64)wr->sg_list[i].addr;
|
|
|
- sge_list[i].len = wr->sg_list[i].length;
|
|
|
+ if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
|
|
|
+ sge_list = hr_qp->rq_inl_buf.wqe_list[ind].sg_list;
|
|
|
+ hr_qp->rq_inl_buf.wqe_list[ind].sge_cnt =
|
|
|
+ (u32)wr->num_sge;
|
|
|
+ for (i = 0; i < wr->num_sge; i++) {
|
|
|
+ sge_list[i].addr =
|
|
|
+ (void *)(u64)wr->sg_list[i].addr;
|
|
|
+ sge_list[i].len = wr->sg_list[i].length;
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
hr_qp->rq.wrid[ind] = wr->wr_id;
|
|
@@ -2169,6 +2173,7 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp,
|
|
|
struct hns_roce_v2_qp_context *context,
|
|
|
struct hns_roce_v2_qp_context *qpc_mask)
|
|
|
{
|
|
|
+ struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
|
|
|
struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
|
|
|
|
|
|
/*
|
|
@@ -2281,7 +2286,8 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp,
|
|
|
context->rq_db_record_addr = hr_qp->rdb.dma >> 32;
|
|
|
qpc_mask->rq_db_record_addr = 0;
|
|
|
|
|
|
- roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 1);
|
|
|
+ roce_set_bit(context->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S,
|
|
|
+ (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) ? 1 : 0);
|
|
|
roce_set_bit(qpc_mask->byte_76_srqn_op_en, V2_QPC_BYTE_76_RQIE_S, 0);
|
|
|
|
|
|
roce_set_field(context->byte_80_rnr_rx_cqn, V2_QPC_BYTE_80_RX_CQN_M,
|