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@@ -414,11 +414,11 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
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return true;
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return true;
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}
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}
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-static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
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+static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
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{mmGB_MACROTILE_MODE7, true},
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{mmGB_MACROTILE_MODE7, true},
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};
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};
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-static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
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+static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
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{mmGB_TILE_MODE7, true},
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{mmGB_TILE_MODE7, true},
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{mmGB_TILE_MODE12, true},
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{mmGB_TILE_MODE12, true},
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{mmGB_TILE_MODE17, true},
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{mmGB_TILE_MODE17, true},
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@@ -426,7 +426,7 @@ static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
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{mmGB_MACROTILE_MODE7, true},
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{mmGB_MACROTILE_MODE7, true},
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};
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};
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-static struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
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+static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
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{mmGRBM_STATUS, false},
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{mmGRBM_STATUS, false},
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{mmGRBM_STATUS2, false},
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{mmGRBM_STATUS2, false},
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{mmGRBM_STATUS_SE0, false},
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{mmGRBM_STATUS_SE0, false},
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@@ -525,8 +525,8 @@ static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
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static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
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static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
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u32 sh_num, u32 reg_offset, u32 *value)
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u32 sh_num, u32 reg_offset, u32 *value)
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{
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{
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- struct amdgpu_allowed_register_entry *asic_register_table = NULL;
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- struct amdgpu_allowed_register_entry *asic_register_entry;
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+ const struct amdgpu_allowed_register_entry *asic_register_table = NULL;
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+ const struct amdgpu_allowed_register_entry *asic_register_entry;
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uint32_t size, i;
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uint32_t size, i;
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*value = 0;
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*value = 0;
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