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@@ -482,17 +482,18 @@
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mstp9_clks: mstp9_clks@e6150994 {
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mstp9_clks: mstp9_clks@e6150994 {
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compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
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compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
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reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
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- clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
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- <&p_clk>, <&p_clk>, <&p_clk>;
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+ clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>,
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+ <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
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+ <&p_clk>;
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#clock-cells = <1>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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renesas,clock-indices = <
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- R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_I2C4
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- R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
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- R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
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+ R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
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+ R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
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+ R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
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>;
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>;
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clock-output-names =
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clock-output-names =
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- "rcan1", "rcan0", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1",
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- "i2c0";
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+ "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
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+ "i2c2", "i2c1", "i2c0";
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};
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};
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mstp11_clks: mstp11_clks@e615099c {
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mstp11_clks: mstp11_clks@e615099c {
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compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
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compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
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