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@@ -27,4 +27,30 @@
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#define EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA only */
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#define EEH_PE_STATE_UNAVAIL 5 /* Unavailable */
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+/* EEH error types and functions */
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+#define EEH_ERR_TYPE_32 0 /* 32-bits error */
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+#define EEH_ERR_TYPE_64 1 /* 64-bits error */
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+#define EEH_ERR_FUNC_MIN 0
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+#define EEH_ERR_FUNC_LD_MEM_ADDR 0 /* Memory load */
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+#define EEH_ERR_FUNC_LD_MEM_DATA 1
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+#define EEH_ERR_FUNC_LD_IO_ADDR 2 /* IO load */
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+#define EEH_ERR_FUNC_LD_IO_DATA 3
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+#define EEH_ERR_FUNC_LD_CFG_ADDR 4 /* Config load */
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+#define EEH_ERR_FUNC_LD_CFG_DATA 5
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+#define EEH_ERR_FUNC_ST_MEM_ADDR 6 /* Memory store */
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+#define EEH_ERR_FUNC_ST_MEM_DATA 7
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+#define EEH_ERR_FUNC_ST_IO_ADDR 8 /* IO store */
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+#define EEH_ERR_FUNC_ST_IO_DATA 9
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+#define EEH_ERR_FUNC_ST_CFG_ADDR 10 /* Config store */
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+#define EEH_ERR_FUNC_ST_CFG_DATA 11
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+#define EEH_ERR_FUNC_DMA_RD_ADDR 12 /* DMA read */
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+#define EEH_ERR_FUNC_DMA_RD_DATA 13
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+#define EEH_ERR_FUNC_DMA_RD_MASTER 14
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+#define EEH_ERR_FUNC_DMA_RD_TARGET 15
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+#define EEH_ERR_FUNC_DMA_WR_ADDR 16 /* DMA write */
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+#define EEH_ERR_FUNC_DMA_WR_DATA 17
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+#define EEH_ERR_FUNC_DMA_WR_MASTER 18
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+#define EEH_ERR_FUNC_DMA_WR_TARGET 19
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+#define EEH_ERR_FUNC_MAX 19
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+
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#endif /* _ASM_POWERPC_EEH_H */
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