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@@ -58,6 +58,12 @@ static void ufs_qcom_dump_regs(struct ufs_hba *hba, int offset, int len,
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len * 4, false);
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len * 4, false);
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}
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}
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+static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,
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+ char *prefix, void *priv)
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+{
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+ ufs_qcom_dump_regs(hba, offset, len, prefix);
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+}
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+
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static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
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static int ufs_qcom_get_connected_tx_lanes(struct ufs_hba *hba, u32 *tx_lanes)
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{
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{
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int err = 0;
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int err = 0;
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@@ -1397,6 +1403,74 @@ out:
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return err;
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return err;
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}
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}
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+static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,
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+ void *priv, void (*print_fn)(struct ufs_hba *hba,
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+ int offset, int num_regs, char *str, void *priv))
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+{
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+ u32 reg;
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+ struct ufs_qcom_host *host;
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+
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+ if (unlikely(!hba)) {
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+ pr_err("%s: hba is NULL\n", __func__);
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+ return;
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+ }
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+ if (unlikely(!print_fn)) {
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+ dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);
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+ return;
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+ }
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+
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+ host = ufshcd_get_variant(hba);
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+ if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))
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+ return;
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+
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+ reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);
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+ print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);
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+
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+ reg = ufshcd_readl(hba, REG_UFS_CFG1);
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+ reg |= UFS_BIT(17);
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+ ufshcd_writel(hba, reg, REG_UFS_CFG1);
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+
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+ reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);
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+ print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);
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+
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+ reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);
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+ print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);
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+
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+ reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);
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+ print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);
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+
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+ ufshcd_writel(hba, (reg & ~UFS_BIT(17)), REG_UFS_CFG1);
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+
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+ reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);
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+ print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);
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+
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+ reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);
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+ print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);
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+
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+ reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);
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+ print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);
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+
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+ reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);
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+ print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);
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+
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+ reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);
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+ print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);
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+
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+ reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);
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+ print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);
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+
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+ reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);
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+ print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);
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+}
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+
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+static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)
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+{
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+ if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
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+ ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);
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+ else
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+ ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);
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+}
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+
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static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
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static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
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{
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{
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/* provide a legal default configuration */
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/* provide a legal default configuration */
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@@ -1505,6 +1579,7 @@ int ufs_qcom_testbus_config(struct ufs_qcom_host *host)
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ufshcd_rmwl(host->hba, mask,
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ufshcd_rmwl(host->hba, mask,
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(u32)host->testbus.select_minor << offset,
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(u32)host->testbus.select_minor << offset,
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reg);
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reg);
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+ ufs_qcom_enable_test_bus(host);
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ufshcd_release(host->hba);
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ufshcd_release(host->hba);
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pm_runtime_put_sync(host->hba->dev);
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pm_runtime_put_sync(host->hba->dev);
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@@ -1521,8 +1596,10 @@ static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)
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ufs_qcom_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16,
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ufs_qcom_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16,
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"HCI Vendor Specific Registers ");
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"HCI Vendor Specific Registers ");
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+ ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);
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ufs_qcom_testbus_read(hba);
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ufs_qcom_testbus_read(hba);
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}
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}
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+
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/**
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/**
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* struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
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* struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
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*
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*
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