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@@ -21,6 +21,8 @@
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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+#include <linux/platform_data/gpio-dwapb.h>
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+#include <linux/slab.h>
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#define GPIO_SWPORTA_DR 0x00
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#define GPIO_SWPORTA_DDR 0x04
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@@ -35,6 +37,7 @@
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#define GPIO_INTTYPE_LEVEL 0x38
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#define GPIO_INT_POLARITY 0x3c
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#define GPIO_INTSTATUS 0x40
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+#define GPIO_PORTA_DEBOUNCE 0x48
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#define GPIO_PORTA_EOI 0x4c
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#define GPIO_EXT_PORTA 0x50
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#define GPIO_EXT_PORTB 0x54
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@@ -48,10 +51,28 @@
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struct dwapb_gpio;
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+#ifdef CONFIG_PM_SLEEP
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+/* Store GPIO context across system-wide suspend/resume transitions */
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+struct dwapb_context {
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+ u32 data;
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+ u32 dir;
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+ u32 ext;
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+ u32 int_en;
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+ u32 int_mask;
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+ u32 int_type;
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+ u32 int_pol;
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+ u32 int_deb;
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+};
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+#endif
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+
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struct dwapb_gpio_port {
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struct bgpio_chip bgc;
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bool is_registered;
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struct dwapb_gpio *gpio;
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+#ifdef CONFIG_PM_SLEEP
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+ struct dwapb_context *ctx;
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+#endif
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+ unsigned int idx;
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};
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struct dwapb_gpio {
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@@ -62,11 +83,33 @@ struct dwapb_gpio {
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struct irq_domain *domain;
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};
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+static inline struct dwapb_gpio_port *
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+to_dwapb_gpio_port(struct bgpio_chip *bgc)
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+{
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+ return container_of(bgc, struct dwapb_gpio_port, bgc);
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+}
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+
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+static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
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+{
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+ struct bgpio_chip *bgc = &gpio->ports[0].bgc;
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+ void __iomem *reg_base = gpio->regs;
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+
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+ return bgc->read_reg(reg_base + offset);
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+}
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+
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+static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
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+ u32 val)
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+{
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+ struct bgpio_chip *bgc = &gpio->ports[0].bgc;
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+ void __iomem *reg_base = gpio->regs;
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+
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+ bgc->write_reg(reg_base + offset, val);
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+}
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+
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static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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- struct dwapb_gpio_port *port = container_of(bgc, struct
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- dwapb_gpio_port, bgc);
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+ struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
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struct dwapb_gpio *gpio = port->gpio;
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return irq_find_mapping(gpio->domain, offset);
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@@ -74,21 +117,20 @@ static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
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{
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- u32 v = readl(gpio->regs + GPIO_INT_POLARITY);
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+ u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);
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if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
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v &= ~BIT(offs);
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else
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v |= BIT(offs);
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- writel(v, gpio->regs + GPIO_INT_POLARITY);
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+ dwapb_write(gpio, GPIO_INT_POLARITY, v);
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}
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-static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
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+static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
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{
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- struct dwapb_gpio *gpio = irq_get_handler_data(irq);
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- struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
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+ u32 ret = irq_status;
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while (irq_status) {
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int hwirq = fls(irq_status) - 1;
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@@ -102,6 +144,16 @@ static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
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dwapb_toggle_trigger(gpio, hwirq);
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}
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+ return ret;
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+}
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+
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+static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
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+{
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+ struct dwapb_gpio *gpio = irq_get_handler_data(irq);
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+ struct irq_chip *chip = irq_desc_get_chip(desc);
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+
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+ dwapb_do_irq(gpio);
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+
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if (chip->irq_eoi)
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chip->irq_eoi(irq_desc_get_irq_data(desc));
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}
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@@ -115,9 +167,9 @@ static void dwapb_irq_enable(struct irq_data *d)
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u32 val;
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spin_lock_irqsave(&bgc->lock, flags);
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- val = readl(gpio->regs + GPIO_INTEN);
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+ val = dwapb_read(gpio, GPIO_INTEN);
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val |= BIT(d->hwirq);
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- writel(val, gpio->regs + GPIO_INTEN);
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+ dwapb_write(gpio, GPIO_INTEN, val);
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spin_unlock_irqrestore(&bgc->lock, flags);
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}
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@@ -130,9 +182,9 @@ static void dwapb_irq_disable(struct irq_data *d)
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u32 val;
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spin_lock_irqsave(&bgc->lock, flags);
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- val = readl(gpio->regs + GPIO_INTEN);
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+ val = dwapb_read(gpio, GPIO_INTEN);
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val &= ~BIT(d->hwirq);
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- writel(val, gpio->regs + GPIO_INTEN);
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+ dwapb_write(gpio, GPIO_INTEN, val);
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spin_unlock_irqrestore(&bgc->lock, flags);
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}
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@@ -172,8 +224,8 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 type)
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return -EINVAL;
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spin_lock_irqsave(&bgc->lock, flags);
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- level = readl(gpio->regs + GPIO_INTTYPE_LEVEL);
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- polarity = readl(gpio->regs + GPIO_INT_POLARITY);
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+ level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
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+ polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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@@ -200,29 +252,55 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 type)
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irq_setup_alt_chip(d, type);
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- writel(level, gpio->regs + GPIO_INTTYPE_LEVEL);
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- writel(polarity, gpio->regs + GPIO_INT_POLARITY);
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+ dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
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+ dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
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+ spin_unlock_irqrestore(&bgc->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
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+ unsigned offset, unsigned debounce)
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+{
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+ struct bgpio_chip *bgc = to_bgpio_chip(gc);
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+ struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
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+ struct dwapb_gpio *gpio = port->gpio;
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+ unsigned long flags, val_deb;
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+ unsigned long mask = bgc->pin2mask(bgc, offset);
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+
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+ spin_lock_irqsave(&bgc->lock, flags);
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+
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+ val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
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+ if (debounce)
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+ dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
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+ else
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+ dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
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+
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spin_unlock_irqrestore(&bgc->lock, flags);
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return 0;
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}
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+static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
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+{
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+ u32 worked;
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+ struct dwapb_gpio *gpio = dev_id;
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+
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+ worked = dwapb_do_irq(gpio);
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+
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+ return worked ? IRQ_HANDLED : IRQ_NONE;
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+}
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+
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static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
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- struct dwapb_gpio_port *port)
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+ struct dwapb_gpio_port *port,
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+ struct dwapb_port_property *pp)
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{
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struct gpio_chip *gc = &port->bgc.gc;
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- struct device_node *node = gc->of_node;
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- struct irq_chip_generic *irq_gc;
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+ struct device_node *node = pp->node;
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+ struct irq_chip_generic *irq_gc = NULL;
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unsigned int hwirq, ngpio = gc->ngpio;
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struct irq_chip_type *ct;
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- int err, irq, i;
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-
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- irq = irq_of_parse_and_map(node, 0);
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- if (!irq) {
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- dev_warn(gpio->dev, "no irq for bank %s\n",
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- port->bgc.gc.of_node->full_name);
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- return;
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- }
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+ int err, i;
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gpio->domain = irq_domain_add_linear(node, ngpio,
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&irq_generic_chip_ops, gpio);
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@@ -269,8 +347,24 @@ static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
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irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
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irq_gc->chip_types[1].handler = handle_edge_irq;
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- irq_set_chained_handler(irq, dwapb_irq_handler);
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- irq_set_handler_data(irq, gpio);
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+ if (!pp->irq_shared) {
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+ irq_set_chained_handler(pp->irq, dwapb_irq_handler);
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+ irq_set_handler_data(pp->irq, gpio);
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+ } else {
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+ /*
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+ * Request a shared IRQ since where MFD would have devices
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+ * using the same irq pin
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+ */
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+ err = devm_request_irq(gpio->dev, pp->irq,
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+ dwapb_irq_handler_mfd,
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+ IRQF_SHARED, "gpio-dwapb-mfd", gpio);
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+ if (err) {
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+ dev_err(gpio->dev, "error requesting IRQ\n");
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+ irq_domain_remove(gpio->domain);
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+ gpio->domain = NULL;
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+ return;
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+ }
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+ }
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for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
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irq_create_mapping(gpio->domain, hwirq);
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@@ -296,57 +390,53 @@ static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
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}
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static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
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- struct device_node *port_np,
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+ struct dwapb_port_property *pp,
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unsigned int offs)
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{
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struct dwapb_gpio_port *port;
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- u32 port_idx, ngpio;
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void __iomem *dat, *set, *dirout;
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int err;
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- if (of_property_read_u32(port_np, "reg", &port_idx) ||
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- port_idx >= DWAPB_MAX_PORTS) {
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- dev_err(gpio->dev, "missing/invalid port index for %s\n",
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- port_np->full_name);
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- return -EINVAL;
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- }
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-
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port = &gpio->ports[offs];
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port->gpio = gpio;
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+ port->idx = pp->idx;
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- if (of_property_read_u32(port_np, "snps,nr-gpios", &ngpio)) {
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- dev_info(gpio->dev, "failed to get number of gpios for %s\n",
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- port_np->full_name);
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- ngpio = 32;
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- }
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+#ifdef CONFIG_PM_SLEEP
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+ port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
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+ if (!port->ctx)
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+ return -ENOMEM;
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+#endif
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- dat = gpio->regs + GPIO_EXT_PORTA + (port_idx * GPIO_EXT_PORT_SIZE);
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- set = gpio->regs + GPIO_SWPORTA_DR + (port_idx * GPIO_SWPORT_DR_SIZE);
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+ dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
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+ set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
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dirout = gpio->regs + GPIO_SWPORTA_DDR +
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- (port_idx * GPIO_SWPORT_DDR_SIZE);
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+ (pp->idx * GPIO_SWPORT_DDR_SIZE);
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err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
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NULL, false);
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if (err) {
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dev_err(gpio->dev, "failed to init gpio chip for %s\n",
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- port_np->full_name);
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+ pp->name);
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return err;
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}
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- port->bgc.gc.ngpio = ngpio;
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- port->bgc.gc.of_node = port_np;
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+#ifdef CONFIG_OF_GPIO
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+ port->bgc.gc.of_node = pp->node;
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+#endif
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+ port->bgc.gc.ngpio = pp->ngpio;
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+ port->bgc.gc.base = pp->gpio_base;
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- /*
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- * Only port A can provide interrupts in all configurations of the IP.
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- */
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- if (port_idx == 0 &&
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- of_property_read_bool(port_np, "interrupt-controller"))
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- dwapb_configure_irqs(gpio, port);
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+ /* Only port A support debounce */
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+ if (pp->idx == 0)
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+ port->bgc.gc.set_debounce = dwapb_gpio_set_debounce;
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+
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+ if (pp->irq)
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+ dwapb_configure_irqs(gpio, port, pp);
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err = gpiochip_add(&port->bgc.gc);
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if (err)
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dev_err(gpio->dev, "failed to register gpiochip for %s\n",
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- port_np->full_name);
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+ pp->name);
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else
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port->is_registered = true;
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@@ -362,25 +452,116 @@ static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
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gpiochip_remove(&gpio->ports[m].bgc.gc);
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}
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+static struct dwapb_platform_data *
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+dwapb_gpio_get_pdata_of(struct device *dev)
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+{
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+ struct device_node *node, *port_np;
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+ struct dwapb_platform_data *pdata;
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+ struct dwapb_port_property *pp;
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+ int nports;
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+ int i;
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+
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+ node = dev->of_node;
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+ if (!IS_ENABLED(CONFIG_OF_GPIO) || !node)
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+ return ERR_PTR(-ENODEV);
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+
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+ nports = of_get_child_count(node);
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+ if (nports == 0)
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+ return ERR_PTR(-ENODEV);
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+
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+ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
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+ if (!pdata)
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+ return ERR_PTR(-ENOMEM);
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+
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+ pdata->properties = kcalloc(nports, sizeof(*pp), GFP_KERNEL);
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+ if (!pdata->properties) {
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+ kfree(pdata);
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+ return ERR_PTR(-ENOMEM);
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+ }
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+
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+ pdata->nports = nports;
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+
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+ i = 0;
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+ for_each_child_of_node(node, port_np) {
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+ pp = &pdata->properties[i++];
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+ pp->node = port_np;
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+
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+ if (of_property_read_u32(port_np, "reg", &pp->idx) ||
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+ pp->idx >= DWAPB_MAX_PORTS) {
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+ dev_err(dev, "missing/invalid port index for %s\n",
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+ port_np->full_name);
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+ kfree(pdata->properties);
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+ kfree(pdata);
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+ return ERR_PTR(-EINVAL);
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+ }
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+
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+ if (of_property_read_u32(port_np, "snps,nr-gpios",
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+ &pp->ngpio)) {
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+ dev_info(dev, "failed to get number of gpios for %s\n",
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|
+ port_np->full_name);
|
|
|
+ pp->ngpio = 32;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Only port A can provide interrupts in all configurations of
|
|
|
+ * the IP.
|
|
|
+ */
|
|
|
+ if (pp->idx == 0 &&
|
|
|
+ of_property_read_bool(port_np, "interrupt-controller")) {
|
|
|
+ pp->irq = irq_of_parse_and_map(port_np, 0);
|
|
|
+ if (!pp->irq) {
|
|
|
+ dev_warn(dev, "no irq for bank %s\n",
|
|
|
+ port_np->full_name);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ pp->irq_shared = false;
|
|
|
+ pp->gpio_base = -1;
|
|
|
+ pp->name = port_np->full_name;
|
|
|
+ }
|
|
|
+
|
|
|
+ return pdata;
|
|
|
+}
|
|
|
+
|
|
|
+static inline void dwapb_free_pdata_of(struct dwapb_platform_data *pdata)
|
|
|
+{
|
|
|
+ if (!IS_ENABLED(CONFIG_OF_GPIO) || !pdata)
|
|
|
+ return;
|
|
|
+
|
|
|
+ kfree(pdata->properties);
|
|
|
+ kfree(pdata);
|
|
|
+}
|
|
|
+
|
|
|
static int dwapb_gpio_probe(struct platform_device *pdev)
|
|
|
{
|
|
|
+ unsigned int i;
|
|
|
struct resource *res;
|
|
|
struct dwapb_gpio *gpio;
|
|
|
- struct device_node *np;
|
|
|
int err;
|
|
|
- unsigned int offs = 0;
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
+ struct dwapb_platform_data *pdata = dev_get_platdata(dev);
|
|
|
+ bool is_pdata_alloc = !pdata;
|
|
|
+
|
|
|
+ if (is_pdata_alloc) {
|
|
|
+ pdata = dwapb_gpio_get_pdata_of(dev);
|
|
|
+ if (IS_ERR(pdata))
|
|
|
+ return PTR_ERR(pdata);
|
|
|
+ }
|
|
|
|
|
|
- gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
|
|
|
- if (!gpio)
|
|
|
- return -ENOMEM;
|
|
|
- gpio->dev = &pdev->dev;
|
|
|
+ if (!pdata->nports) {
|
|
|
+ err = -ENODEV;
|
|
|
+ goto out_err;
|
|
|
+ }
|
|
|
|
|
|
- gpio->nr_ports = of_get_child_count(pdev->dev.of_node);
|
|
|
- if (!gpio->nr_ports) {
|
|
|
- err = -EINVAL;
|
|
|
+ gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
|
|
|
+ if (!gpio) {
|
|
|
+ err = -ENOMEM;
|
|
|
goto out_err;
|
|
|
}
|
|
|
- gpio->ports = devm_kzalloc(&pdev->dev, gpio->nr_ports *
|
|
|
+ gpio->dev = &pdev->dev;
|
|
|
+ gpio->nr_ports = pdata->nports;
|
|
|
+
|
|
|
+ gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
|
|
|
sizeof(*gpio->ports), GFP_KERNEL);
|
|
|
if (!gpio->ports) {
|
|
|
err = -ENOMEM;
|
|
@@ -394,20 +575,23 @@ static int dwapb_gpio_probe(struct platform_device *pdev)
|
|
|
goto out_err;
|
|
|
}
|
|
|
|
|
|
- for_each_child_of_node(pdev->dev.of_node, np) {
|
|
|
- err = dwapb_gpio_add_port(gpio, np, offs++);
|
|
|
+ for (i = 0; i < gpio->nr_ports; i++) {
|
|
|
+ err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
|
|
|
if (err)
|
|
|
goto out_unregister;
|
|
|
}
|
|
|
platform_set_drvdata(pdev, gpio);
|
|
|
|
|
|
- return 0;
|
|
|
+ goto out_err;
|
|
|
|
|
|
out_unregister:
|
|
|
dwapb_gpio_unregister(gpio);
|
|
|
dwapb_irq_teardown(gpio);
|
|
|
|
|
|
out_err:
|
|
|
+ if (is_pdata_alloc)
|
|
|
+ dwapb_free_pdata_of(pdata);
|
|
|
+
|
|
|
return err;
|
|
|
}
|
|
|
|
|
@@ -427,10 +611,100 @@ static const struct of_device_id dwapb_of_match[] = {
|
|
|
};
|
|
|
MODULE_DEVICE_TABLE(of, dwapb_of_match);
|
|
|
|
|
|
+#ifdef CONFIG_PM_SLEEP
|
|
|
+static int dwapb_gpio_suspend(struct device *dev)
|
|
|
+{
|
|
|
+ struct platform_device *pdev = to_platform_device(dev);
|
|
|
+ struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
|
|
|
+ struct bgpio_chip *bgc = &gpio->ports[0].bgc;
|
|
|
+ unsigned long flags;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ spin_lock_irqsave(&bgc->lock, flags);
|
|
|
+ for (i = 0; i < gpio->nr_ports; i++) {
|
|
|
+ unsigned int offset;
|
|
|
+ unsigned int idx = gpio->ports[i].idx;
|
|
|
+ struct dwapb_context *ctx = gpio->ports[i].ctx;
|
|
|
+
|
|
|
+ BUG_ON(!ctx);
|
|
|
+
|
|
|
+ offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
|
|
|
+ ctx->dir = dwapb_read(gpio, offset);
|
|
|
+
|
|
|
+ offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
|
|
|
+ ctx->data = dwapb_read(gpio, offset);
|
|
|
+
|
|
|
+ offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
|
|
|
+ ctx->ext = dwapb_read(gpio, offset);
|
|
|
+
|
|
|
+ /* Only port A can provide interrupts */
|
|
|
+ if (idx == 0) {
|
|
|
+ ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
|
|
|
+ ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
|
|
|
+ ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
|
|
|
+ ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
|
|
|
+ ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
|
|
|
+
|
|
|
+ /* Mask out interrupts */
|
|
|
+ dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ spin_unlock_irqrestore(&bgc->lock, flags);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int dwapb_gpio_resume(struct device *dev)
|
|
|
+{
|
|
|
+ struct platform_device *pdev = to_platform_device(dev);
|
|
|
+ struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
|
|
|
+ struct bgpio_chip *bgc = &gpio->ports[0].bgc;
|
|
|
+ unsigned long flags;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ spin_lock_irqsave(&bgc->lock, flags);
|
|
|
+ for (i = 0; i < gpio->nr_ports; i++) {
|
|
|
+ unsigned int offset;
|
|
|
+ unsigned int idx = gpio->ports[i].idx;
|
|
|
+ struct dwapb_context *ctx = gpio->ports[i].ctx;
|
|
|
+
|
|
|
+ BUG_ON(!ctx);
|
|
|
+
|
|
|
+ offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
|
|
|
+ dwapb_write(gpio, offset, ctx->data);
|
|
|
+
|
|
|
+ offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
|
|
|
+ dwapb_write(gpio, offset, ctx->dir);
|
|
|
+
|
|
|
+ offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
|
|
|
+ dwapb_write(gpio, offset, ctx->ext);
|
|
|
+
|
|
|
+ /* Only port A can provide interrupts */
|
|
|
+ if (idx == 0) {
|
|
|
+ dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
|
|
|
+ dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
|
|
|
+ dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
|
|
|
+ dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
|
|
|
+ dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
|
|
|
+
|
|
|
+ /* Clear out spurious interrupts */
|
|
|
+ dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ spin_unlock_irqrestore(&bgc->lock, flags);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
+static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
|
|
|
+ dwapb_gpio_resume);
|
|
|
+
|
|
|
static struct platform_driver dwapb_gpio_driver = {
|
|
|
.driver = {
|
|
|
.name = "gpio-dwapb",
|
|
|
.owner = THIS_MODULE,
|
|
|
+ .pm = &dwapb_gpio_pm_ops,
|
|
|
.of_match_table = of_match_ptr(dwapb_of_match),
|
|
|
},
|
|
|
.probe = dwapb_gpio_probe,
|