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@@ -55,6 +55,7 @@
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#define TLP_CFG_DW2(bus, devfn, offset) \
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#define TLP_CFG_DW2(bus, devfn, offset) \
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(((bus) << 24) | ((devfn) << 16) | (offset))
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(((bus) << 24) | ((devfn) << 16) | (offset))
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#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
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#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
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+#define TLP_COMP_STATUS(s) (((s) >> 12) & 7)
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#define TLP_HDR_SIZE 3
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#define TLP_HDR_SIZE 3
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#define TLP_LOOP 500
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#define TLP_LOOP 500
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#define RP_DEVFN 0
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#define RP_DEVFN 0
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@@ -171,6 +172,7 @@ static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
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bool sop = 0;
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bool sop = 0;
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u32 ctrl;
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u32 ctrl;
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u32 reg0, reg1;
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u32 reg0, reg1;
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+ u32 comp_status = 1;
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/*
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/*
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* Minimum 2 loops to read TLP headers and 1 loop to read data
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* Minimum 2 loops to read TLP headers and 1 loop to read data
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@@ -182,19 +184,25 @@ static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
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reg0 = cra_readl(pcie, RP_RXCPL_REG0);
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reg0 = cra_readl(pcie, RP_RXCPL_REG0);
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reg1 = cra_readl(pcie, RP_RXCPL_REG1);
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reg1 = cra_readl(pcie, RP_RXCPL_REG1);
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- if (ctrl & RP_RXCPL_SOP)
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+ if (ctrl & RP_RXCPL_SOP) {
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sop = true;
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sop = true;
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+ comp_status = TLP_COMP_STATUS(reg1);
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+ }
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if (ctrl & RP_RXCPL_EOP) {
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if (ctrl & RP_RXCPL_EOP) {
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+ if (comp_status)
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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if (value)
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if (value)
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*value = reg0;
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*value = reg0;
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+
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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}
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}
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}
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}
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udelay(5);
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udelay(5);
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}
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}
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- return -ENOENT;
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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}
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}
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static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
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static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
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