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@@ -635,7 +635,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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int r, i;
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- unsigned fpfn, lpfn;
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if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
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return -EPERM;
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@@ -667,22 +666,16 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
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}
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bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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+ /* force to pin into visible video ram */
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+ if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
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+ bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
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amdgpu_ttm_placement_from_domain(bo, domain);
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for (i = 0; i < bo->placement.num_placement; i++) {
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- /* force to pin into visible video ram */
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- if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
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- !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
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- (!max_offset || max_offset >
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- adev->mc.visible_vram_size)) {
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- if (WARN_ON_ONCE(min_offset >
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- adev->mc.visible_vram_size))
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- return -EINVAL;
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- fpfn = min_offset >> PAGE_SHIFT;
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- lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
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- } else {
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- fpfn = min_offset >> PAGE_SHIFT;
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- lpfn = max_offset >> PAGE_SHIFT;
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- }
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+ unsigned fpfn, lpfn;
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+
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+ fpfn = min_offset >> PAGE_SHIFT;
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+ lpfn = max_offset >> PAGE_SHIFT;
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+
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if (fpfn > bo->placements[i].fpfn)
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bo->placements[i].fpfn = fpfn;
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if (!bo->placements[i].lpfn ||
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