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@@ -1054,21 +1054,6 @@ gen6_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
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GEN6_WRITE_FOOTER; \
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}
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-#define __hsw_write(x) \
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-static void \
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-hsw_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
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- u32 __fifo_ret = 0; \
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- GEN6_WRITE_HEADER; \
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- if (NEEDS_FORCE_WAKE(offset)) { \
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- __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
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- } \
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- __raw_i915_write##x(dev_priv, reg, val); \
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- if (unlikely(__fifo_ret)) { \
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- gen6_gt_check_fifodbg(dev_priv); \
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- } \
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- GEN6_WRITE_FOOTER; \
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-}
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-
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#define __gen8_write(x) \
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static void \
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gen8_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool trace) { \
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@@ -1115,9 +1100,6 @@ __chv_write(32)
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__gen8_write(8)
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__gen8_write(16)
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__gen8_write(32)
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-__hsw_write(8)
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-__hsw_write(16)
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-__hsw_write(32)
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__gen6_write(8)
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__gen6_write(16)
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__gen6_write(32)
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@@ -1125,7 +1107,6 @@ __gen6_write(32)
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#undef __gen9_write
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#undef __chv_write
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#undef __gen8_write
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-#undef __hsw_write
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#undef __gen6_write
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#undef GEN6_WRITE_FOOTER
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#undef GEN6_WRITE_HEADER
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@@ -1342,11 +1323,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
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break;
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case 7:
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case 6:
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- if (IS_HASWELL(dev_priv)) {
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- ASSIGN_WRITE_MMIO_VFUNCS(hsw);
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- } else {
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- ASSIGN_WRITE_MMIO_VFUNCS(gen6);
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- }
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+ ASSIGN_WRITE_MMIO_VFUNCS(gen6);
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if (IS_VALLEYVIEW(dev_priv)) {
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ASSIGN_READ_MMIO_VFUNCS(vlv);
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