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@@ -220,15 +220,6 @@ static struct event_constraint intel_hsw_event_constraints[] = {
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EVENT_CONSTRAINT_END
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};
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-static struct event_constraint intel_bdw_event_constraints[] = {
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- FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
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- FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
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- FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
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- INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
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- INTEL_EVENT_CONSTRAINT(0xa3, 0x4), /* CYCLE_ACTIVITY.* */
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- EVENT_CONSTRAINT_END
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-};
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-
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static u64 intel_pmu_event_map(int hw_event)
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{
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return intel_perfmon_event_map[hw_event];
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@@ -424,126 +415,6 @@ static __initconst const u64 snb_hw_cache_event_ids
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};
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-static __initconst const u64 hsw_hw_cache_event_ids
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- [PERF_COUNT_HW_CACHE_MAX]
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- [PERF_COUNT_HW_CACHE_OP_MAX]
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- [PERF_COUNT_HW_CACHE_RESULT_MAX] =
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-{
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- [ C(L1D ) ] = {
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- [ C(OP_READ) ] = {
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- [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
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- [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
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- },
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- [ C(OP_WRITE) ] = {
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- [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
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- [ C(RESULT_MISS) ] = 0x0,
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- },
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- [ C(OP_PREFETCH) ] = {
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- [ C(RESULT_ACCESS) ] = 0x0,
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- [ C(RESULT_MISS) ] = 0x0,
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- },
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- },
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- [ C(L1I ) ] = {
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- [ C(OP_READ) ] = {
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- [ C(RESULT_ACCESS) ] = 0x0,
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- [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
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- },
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- [ C(OP_WRITE) ] = {
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- [ C(RESULT_ACCESS) ] = -1,
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- [ C(RESULT_MISS) ] = -1,
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- },
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- [ C(OP_PREFETCH) ] = {
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- [ C(RESULT_ACCESS) ] = 0x0,
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- [ C(RESULT_MISS) ] = 0x0,
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- },
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- },
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- [ C(LL ) ] = {
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- [ C(OP_READ) ] = {
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- /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD */
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- [ C(RESULT_ACCESS) ] = 0x1b7,
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- /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD|SUPPLIER_NONE|
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- L3_MISS|ANY_SNOOP */
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- [ C(RESULT_MISS) ] = 0x1b7,
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- },
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- [ C(OP_WRITE) ] = {
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- [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE:ALL_RFO */
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- /* OFFCORE_RESPONSE:ALL_RFO|SUPPLIER_NONE|L3_MISS|ANY_SNOOP */
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- [ C(RESULT_MISS) ] = 0x1b7,
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- },
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- [ C(OP_PREFETCH) ] = {
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- [ C(RESULT_ACCESS) ] = 0x0,
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- [ C(RESULT_MISS) ] = 0x0,
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- },
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- },
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- [ C(DTLB) ] = {
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- [ C(OP_READ) ] = {
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- [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
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- [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
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- },
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- [ C(OP_WRITE) ] = {
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- [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
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- [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
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- },
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- [ C(OP_PREFETCH) ] = {
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- [ C(RESULT_ACCESS) ] = 0x0,
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- [ C(RESULT_MISS) ] = 0x0,
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- },
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- },
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- [ C(ITLB) ] = {
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- [ C(OP_READ) ] = {
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- [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
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- [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
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- },
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- [ C(OP_WRITE) ] = {
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- [ C(RESULT_ACCESS) ] = -1,
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- [ C(RESULT_MISS) ] = -1,
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- },
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- [ C(OP_PREFETCH) ] = {
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- [ C(RESULT_ACCESS) ] = -1,
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- [ C(RESULT_MISS) ] = -1,
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- },
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- },
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- [ C(BPU ) ] = {
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- [ C(OP_READ) ] = {
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- [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
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- [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
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- },
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- [ C(OP_WRITE) ] = {
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- [ C(RESULT_ACCESS) ] = -1,
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- [ C(RESULT_MISS) ] = -1,
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- },
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- [ C(OP_PREFETCH) ] = {
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- [ C(RESULT_ACCESS) ] = -1,
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- [ C(RESULT_MISS) ] = -1,
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- },
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- },
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-};
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-
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-static __initconst const u64 hsw_hw_cache_extra_regs
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- [PERF_COUNT_HW_CACHE_MAX]
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- [PERF_COUNT_HW_CACHE_OP_MAX]
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- [PERF_COUNT_HW_CACHE_RESULT_MAX] =
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-{
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- [ C(LL ) ] = {
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- [ C(OP_READ) ] = {
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- /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD */
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- [ C(RESULT_ACCESS) ] = 0x2d5,
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- /* OFFCORE_RESPONSE:ALL_DATA_RD|ALL_CODE_RD|SUPPLIER_NONE|
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- L3_MISS|ANY_SNOOP */
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- [ C(RESULT_MISS) ] = 0x3fbc0202d5ull,
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- },
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- [ C(OP_WRITE) ] = {
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- [ C(RESULT_ACCESS) ] = 0x122, /* OFFCORE_RESPONSE:ALL_RFO */
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- /* OFFCORE_RESPONSE:ALL_RFO|SUPPLIER_NONE|L3_MISS|ANY_SNOOP */
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- [ C(RESULT_MISS) ] = 0x3fbc020122ull,
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- },
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- [ C(OP_PREFETCH) ] = {
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- [ C(RESULT_ACCESS) ] = 0x0,
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- [ C(RESULT_MISS) ] = 0x0,
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- },
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- },
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-};
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-
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static __initconst const u64 westmere_hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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@@ -2034,24 +1905,6 @@ hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
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return c;
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}
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-/*
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- * Broadwell:
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- * The INST_RETIRED.ALL period always needs to have lowest
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- * 6bits cleared (BDM57). It shall not use a period smaller
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- * than 100 (BDM11). We combine the two to enforce
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- * a min-period of 128.
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- */
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-static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
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-{
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- if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
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- X86_CONFIG(.event=0xc0, .umask=0x01)) {
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- if (left < 128)
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- left = 128;
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- left &= ~0x3fu;
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- }
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- return left;
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-}
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-
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PMU_FORMAT_ATTR(event, "config:0-7" );
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PMU_FORMAT_ATTR(umask, "config:8-15" );
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PMU_FORMAT_ATTR(edge, "config:18" );
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@@ -2692,8 +2545,8 @@ __init int intel_pmu_init(void)
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case 69: /* 22nm Haswell ULT */
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case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
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x86_pmu.late_ack = true;
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- memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
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- memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
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+ memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
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+ memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
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intel_pmu_lbr_init_snb();
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@@ -2712,28 +2565,6 @@ __init int intel_pmu_init(void)
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pr_cont("Haswell events, ");
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break;
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- case 61: /* 14nm Broadwell Core-M */
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- x86_pmu.late_ack = true;
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- memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
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- memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
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-
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- intel_pmu_lbr_init_snb();
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-
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- x86_pmu.event_constraints = intel_bdw_event_constraints;
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- x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
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- x86_pmu.extra_regs = intel_snbep_extra_regs;
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- x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
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- /* all extra regs are per-cpu when HT is on */
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- x86_pmu.er_flags |= ERF_HAS_RSP_1;
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- x86_pmu.er_flags |= ERF_NO_HT_SHARING;
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-
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- x86_pmu.hw_config = hsw_hw_config;
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- x86_pmu.get_event_constraints = hsw_get_event_constraints;
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- x86_pmu.cpu_events = hsw_events_attrs;
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- x86_pmu.limit_period = bdw_limit_period;
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- pr_cont("Broadwell events, ");
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- break;
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-
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default:
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switch (x86_pmu.version) {
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case 1:
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