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@@ -238,8 +238,10 @@
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linux,pci-domain = <0>;
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linux,pci-domain = <0>;
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max-link-speed = <1>;
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max-link-speed = <1>;
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msi-map = <0x0 &its 0x0 0x1000>;
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msi-map = <0x0 &its 0x0 0x1000>;
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- phys = <&pcie_phy>;
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- phy-names = "pcie-phy";
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+ phys = <&pcie_phy 0>, <&pcie_phy 1>,
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+ <&pcie_phy 2>, <&pcie_phy 3>;
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+ phy-names = "pcie-phy-0", "pcie-phy-1",
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+ "pcie-phy-2", "pcie-phy-3";
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ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
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ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000
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0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
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0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
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resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
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@@ -1295,7 +1297,7 @@
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compatible = "rockchip,rk3399-pcie-phy";
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compatible = "rockchip,rk3399-pcie-phy";
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clocks = <&cru SCLK_PCIEPHY_REF>;
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clocks = <&cru SCLK_PCIEPHY_REF>;
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clock-names = "refclk";
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clock-names = "refclk";
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- #phy-cells = <0>;
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+ #phy-cells = <1>;
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resets = <&cru SRST_PCIEPHY>;
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resets = <&cru SRST_PCIEPHY>;
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reset-names = "phy";
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reset-names = "phy";
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status = "disabled";
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status = "disabled";
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