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@@ -76,7 +76,8 @@
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#define NDCR_ND_MODE (0x3 << 21)
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#define NDCR_NAND_MODE (0x0)
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#define NDCR_CLR_PG_CNT (0x1 << 20)
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-#define NDCR_STOP_ON_UNCOR (0x1 << 19)
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+#define NFCV1_NDCR_ARB_CNTL (0x1 << 19)
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+#define NFCV2_NDCR_STOP_ON_UNCOR (0x1 << 19)
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#define NDCR_RD_ID_CNT_MASK (0x7 << 16)
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#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
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@@ -1320,7 +1321,8 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
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/* Set an initial chunk size */
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info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
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- info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
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+ info->reg_ndcr = ndcr &
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+ ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);
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info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
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info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
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return 0;
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@@ -1553,6 +1555,7 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
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pxa3xx_flash_ids[1].name = NULL;
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def = pxa3xx_flash_ids;
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KEEP_CONFIG:
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+ info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
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if (info->reg_ndcr & NDCR_DWIDTH_M)
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chip->options |= NAND_BUSWIDTH_16;
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@@ -1768,6 +1771,16 @@ static int pxa3xx_nand_remove(struct platform_device *pdev)
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free_irq(irq, info);
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pxa3xx_nand_free_buff(info);
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+ /*
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+ * In the pxa3xx case, the DFI bus is shared between the SMC and NFC.
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+ * In order to prevent a lockup of the system bus, the DFI bus
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+ * arbitration is granted to SMC upon driver removal. This is done by
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+ * setting the x_ARB_CNTL bit, which also prevents the NAND to have
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+ * access to the bus anymore.
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+ */
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+ nand_writel(info, NDCR,
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+ (nand_readl(info, NDCR) & ~NDCR_ND_ARB_EN) |
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+ NFCV1_NDCR_ARB_CNTL);
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clk_disable_unprepare(info->clk);
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for (cs = 0; cs < pdata->num_cs; cs++)
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