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@@ -24,6 +24,7 @@
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#include <asm/pgtable.h>
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#include <asm/cacheflush.h>
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#include <asm/tlb.h>
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+#include <asm/tlbdebug.h>
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#undef CONFIG_MIPS_MT
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#include <asm/r4kcache.h>
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@@ -60,50 +61,15 @@ inline u32 kvm_mips_get_commpage_asid(struct kvm_vcpu *vcpu)
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void kvm_mips_dump_host_tlbs(void)
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{
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- unsigned long old_entryhi;
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- unsigned long old_pagemask;
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- struct kvm_mips_tlb tlb;
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unsigned long flags;
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- int i;
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local_irq_save(flags);
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- old_entryhi = read_c0_entryhi();
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- old_pagemask = read_c0_pagemask();
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-
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kvm_info("HOST TLBs:\n");
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- kvm_info("ASID: %#lx\n", read_c0_entryhi() &
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- cpu_asid_mask(¤t_cpu_data));
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+ dump_tlb_regs();
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+ pr_info("\n");
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+ dump_tlb_all();
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- for (i = 0; i < current_cpu_data.tlbsize; i++) {
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- write_c0_index(i);
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- mtc0_tlbw_hazard();
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-
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- tlb_read();
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- tlbw_use_hazard();
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-
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- tlb.tlb_hi = read_c0_entryhi();
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- tlb.tlb_lo0 = read_c0_entrylo0();
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- tlb.tlb_lo1 = read_c0_entrylo1();
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- tlb.tlb_mask = read_c0_pagemask();
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-
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- kvm_info("TLB%c%3d Hi 0x%08lx ",
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- (tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*',
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- i, tlb.tlb_hi);
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- kvm_info("Lo0=0x%09llx %c%c attr %lx ",
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- (u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo0),
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- (tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ',
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- (tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ',
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- (tlb.tlb_lo0 >> 3) & 7);
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- kvm_info("Lo1=0x%09llx %c%c attr %lx sz=%lx\n",
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- (u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo1),
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- (tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ',
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- (tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ',
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- (tlb.tlb_lo1 >> 3) & 7, tlb.tlb_mask);
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- }
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- write_c0_entryhi(old_entryhi);
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- write_c0_pagemask(old_pagemask);
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- mtc0_tlbw_hazard();
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL_GPL(kvm_mips_dump_host_tlbs);
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