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@@ -35,15 +35,25 @@
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* U = Unused. *
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************************************************************************/
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+/*
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+ * txrx : WR RHR/THR - Holding reg
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+ * ier : WR IER - Interrupt Enable Reg
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+ * isr_fcr : WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg
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+ * lcr : WR LCR - Line Control Reg
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+ * mcr : WR MCR - Modem Control Reg
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+ * lsr : WR LSR - Line Status Reg
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+ * msr : WR MSG - Modem Status Reg
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+ * spr : WR SPR - Scratch pad Reg
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+ */
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struct cls_uart_struct {
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- u8 txrx; /* WR RHR/THR - Holding Reg */
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- u8 ier; /* WR IER - Interrupt Enable Reg */
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- u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
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- u8 lcr; /* WR LCR - Line Control Reg */
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- u8 mcr; /* WR MCR - Modem Control Reg */
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- u8 lsr; /* WR LSR - Line Status Reg */
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- u8 msr; /* WR MSR - Modem Status Reg */
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- u8 spr; /* WR SPR - Scratch Pad Reg */
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+ u8 txrx;
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+ u8 ier;
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+ u8 isr_fcr;
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+ u8 lcr;
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+ u8 mcr;
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+ u8 lsr;
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+ u8 msr;
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+ u8 spr;
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};
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/* Where to read the interrupt register (8bits) */
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@@ -61,8 +71,11 @@ struct cls_uart_struct {
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#define UART_16654_FCR_RXTRIGGER_56 0x80
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#define UART_16654_FCR_RXTRIGGER_60 0xC0
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-#define UART_IIR_CTSRTS 0x20 /* Received CTS/RTS change of state */
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-#define UART_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
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+/* Received CTS/RTS change of state */
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+#define UART_IIR_CTSRTS 0x20
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+
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+/* Receiver data TIMEOUT */
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+#define UART_IIR_RDI_TIMEOUT 0x0C
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/*
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* These are the EXTENDED definitions for the Exar 654's Interrupt
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@@ -74,8 +87,11 @@ struct cls_uart_struct {
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#define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
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#define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
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-#define UART_EXAR654_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
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-#define UART_EXAR654_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
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+/* Indicates whether chip saw an incoming XOFF char */
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+#define UART_EXAR654_XOFF_DETECT 0x1
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+
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+/* Indicates whether chip saw an incoming XON char */
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+#define UART_EXAR654_XON_DETECT 0x2
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#define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */
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#define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */
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